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AS3675 Datasheet(PDF) 51 Page - ams AG |
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AS3675 Datasheet(HTML) 51 Page - ams AG |
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51 / 81 page ![]() www.austriamicrosystems.com/AS3675 1v3 50 - 80 AS3675 Datasheet - D e ta i l e d D e s c r i p t i o n 4 gpi_rgb3_en 0R/W Enables the RGB3 input 0 input disabled 1 input enabled 5 gpi_curr41_en 0R/W Enables the CURR41 input 0 input disabled 1 input enabled 6 gpi_curr42_en 0R/W Enables the CURR42 input 0 input disabled 1 input enabled 7 gpi_curr43_en 0R/W Enables the CURR43 input 0 input disabled 1 input enabled Table 71. GPIO signal 2 Register Addr: 51h GPIO signal 2 This register controls GPIO outputs. Bit Bit Name Default Access Description 0 gpio _in N/A R Reads a logic signal from pin GPIO; this is independent of any other setting e.g.,Table 72 except gpio_pulls=11 1 gpi_ in N/A R Reads a logic signal from pin VANA/GPI; if gpi_en=1 2 gpi_rgb1_in N/A R Reads a logic signal from pin RGB1; if gpi_rgb1_en=1 3 gpi_rgb2_in N/A R Reads a logic signal from pin RGB2; if gpi_rgb2_en=1 4 gpi_rgb3_in N/A R Reads a logic signal from pin RGB3; if gpi_rgb3_en=1 5 gpi_curr41_in N/A R Reads a logic signal from pin CURR41; if gpi_curr41_en=1 6 gpi_curr42_in N/A R Reads a logic signal from pin CURR42; if gpi_curr42_en=1 7 gpi_curr43_in N/A R Reads a logic signal from pin CURR43; if gpi_curr43_en=1 Table 72. GPIO control Register Addr: 1Eh GPIO control This register controls GPIO and GPIO1 pin functions. Bit Bit Name Default Access Description 1:0 gpio_mode 00 R/W Defines the direction for pin GPIO 00 Input only 01 Output (push and pull) 10 Output (open drain, only push; only NMOS is active) 11 Output (open drain, only pull; only PMOS is active) Table 70. GPIO output 2 Register (Continued) Addr: 50h GPIO output 2 This register controls GPIO outputs. Bit Bit Name Default Access Description |
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