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TSL2771 Datasheet(PDF) 25 Page - ams AG

Part # TSL2771
Description  LIGHT-TO-DIGITAL CONVERTER with PROXIMITY SENSING
PDF  33 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

TSL2771 Datasheet(HTML) 25 Page - ams AG

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TSL2771
LIGHT-TO-DIGITAL CONVERTER
with PROXIMITY SENSING
TAOS100B − FEBRUARY 2011
24
r
r
Copyright
E 2011, TAOS Inc.
The LUMENOLOGY
r Company
www.taosinc.com
Status Register (0x13)
The Status Register provides the internal status of the device. This register is read only.
Table 14. Status Register
6
75
4
AVALID
2
31
0
STATUS
Reserved
Resv
AINT
Address
0x13
Reserved
PINT
FIELD
BIT
DESCRIPTION
Reserved
7:6
Reserved.
PINT
5
Proximity Interrupt. Indicates that the device is asserting a proximity interrupt.
AINT
4
ALS Interrupt. Indicates that the device is asserting an ALS interrupt.
Reserved
3:1
Reserved.
AVALID
0
ALS Valid. Indicates that the ALS channels have completed an integration cycle.
ADC Channel Data Registers (0x14 − 0x17)
ALS data is stored as two 16-bit values. To ensure the data is read correctly, a two-byte read I2C transaction
should be used with auto increment protocol bits set in the command register. With this operation, when the
lower byte register is read, the upper eight bits are stored in a shadow register, which is read by a subsequent
read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles
end between the reading of the lower and upper registers.
Table 15. ADC Channel Data Registers
REGISTER
ADDRESS
BITS
DESCRIPTION
C0DATA
0x14
7:0
ALS CH0 data low byte
C0DATAH
0x15
7:0
ALS CH0 data high byte
C1DATA
0x16
7:0
ALS CH1 data low byte
C1DATAH
0x17
7:0
ALS CH1 data high byte
Proximity Data Registers (0x18 − 0x19)
Proximity data is stored as a 16-bit value. To ensure the data is read correctly, a two-byte read I2C transaction
should be utilized with auto increment protocol bits set in the command register. With this operation, when the
lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent
read to the upper byte. The upper register will read the correct value even if the next ADC cycle ends between
the reading of the lower and upper registers.
Table 16.
PDATA Registers
REGISTER
ADDRESS
BITS
DESCRIPTION
PDATAL
0x18
7:0
Proximity data low byte
PDATAH
0x19
7:0
Proximity data high byte



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