T5743 datasheet(20/41 Pages) ATMEL

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T5743

4569A–RKE–12/02

Figure 24. Data Clock Disappears Because of a Logical Error

Figure 25. Output of the Data Clock After a Successful Bit Check

The delay of the data clock is calculated as follows:

Delay = tDelay1 + tDelay2

Delay1 is the delay between the internal signals Data_Out and Data_In. For the rising

edge, t

Delay1 depends on the capacitive load CL at Pin DATA and the external pull-up

resistor R

pup. For the falling edge, tDelay1 depends additionally on the external voltage VX

(see Figure 26, Figure 27 and Figure 34). When the level of Data_In is equal to the level

of Data_Out, the data clock is issued after an additional delay t

Delay2.

Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive

load at Pin DATA is exceeded, the data clock disappears (see section “Data Interface”).

Dem_out

Data_out (DATA)

DATA_CLK

'1'

'0'

'1'

'?'

'0'

'1'

'0'

Logical error (Manchester code violation)

Data

Receiving mode,

bit check aktive

Receiving mode,

data clock control

logic active

Dem_out

Data_out (DATA)

DATA_CLK

'1'

'0'

'1'

'0'

'1'

'0'

Bit check ok

Data

Receiving mode,

bit check active

Receiving mode,

data clock control

logic active

Start bit

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