T5743 datasheet(21/41 Pages) ATMEL

21 / 41 page

T5743

4569A–RKE–12/02

Figure 26. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)

Figure 27. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)

Digital Noise

Suppression

After a data transmission, digital noise appears on the data output (see Figure 28). To

prevent that digital noise keeps the connected microcontroller busy, it can be sup-

pressed in two different ways.

Automatic Noise Suppression

(see Figure 29)

If the bit Noise_Disable (Table 10) in the OPMODE register is set to 1 (default), the

receiver changes to bit-check mode at the end of a valid data stream. The digital noise

is suppressed and the level at Pin DATA is High in that case. The receiver changes

back to receiving mode, if the bit check was successful.

This way to suppress the noise is recommended if the data stream is Manchester or Bi-

phase coded and is active after power on.

Figure 30 illustrates the behavior of the data output at the end of a data stream. Note

that if the last period of the data stream is a high period (rising edge to falling edge), a

pulse occurs on Pin DATA. The length of the pulse depends on the selected baud-rate

range.

V Il = 0,35 * V S

Ih = 0,65 * V

DATA_CLK

Serial bi-directional

data line

Delay1

P_Data_Clk

Data_Out

Data_In

Delay2

Delay

Il = 0,35 * V S

Ih = 0,65 * V S

DATA_CLK

Serial bi-directional

data line

Delay1

P_Data_Clk

Data_Out

Data_In

Delay2

Delay

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