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LDAC Functionality

DAC8574 Registers

DAC8574 as a Slave Receiver - Standard and Fast Mode

SLAVE ADDRESS R/W

A Ctrl-Byte

A MS-Byte A

LS-Byte

A/A

”0” (write)

Data Transferred

(n* Words + Acknowledge)

Word = 16 Bit

From Master to DAC8574

From DAC8574 to Master

A = Acknowledge (SDA LOW)

A = Not Acknowledge (SDA HIGH)

S = START Condition

Sr = Repeated START Condition

P = STOP Condition

DAC8574 I2C-SLAVE ADDRESS:

R/W

MSB

LSB

Factory Preset

A0 = I2C Address Pin

A1 = I2C Address Pin

‘0’ = Write to DAC8574

‘1’ = Read from DAC8574

DAC8574

SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004

Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal

that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the

channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four

DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only

be used after the buffers temporary registers are properly updated through software.

Table 3. DAC8574 Architecture Register Descriptions

Description

CTRL[7:0]

Stores 8-bit wide control byte sent by the master

Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit

MSB[7:0]

power-down data.

LSB[7:0]

Stores the 8 least significant bits of unsigned binary data sent by the master.

TRA[17:0], TRB[17:0],

18-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 16

TRC[17:0], TRD[17:0]

LSBs store data.

DRA[17:0], DRB[17:0],

18-bit DAC registers for each channel. Two MSBs store power-down information, 16 LSBs store DAC data.

DRC[17:0], DRD[17:0]

An update of this register means a DAC update with data or power-down.

Figure 51 shows the standard and fast mode master transmitter addressing a DAC8574 Slave Receiver with a

7-bit address.

Figure 51. Standard and Fast Mode: Slave Receiver

DAC8574IPWR Datasheet(PDF) 20 Page - Texas Instruments

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