Ver1.0

31

LD1072

16-CH LED DRIVER WITH DOT CORRECTION AND 12-BIT PWM CONTROL

GRAYSCALE PWM OPERATION

The grayscale PWM cycle starts with the falling edge of OEB. The first PWMCLK pulse after OEB goes low

increases the PWM counter by one and switches on all OUTn with PWM value not zero. Each following rising

edge of PWMCLK increases the PWM counter by one. The LD1072 compares the PWM value of each output

OUTn with the PWM counter value. All OUTn with PWM values equal to the counter values are switched off. A

OEB=H signal after 4096 PWMCLK pulses resets the PWM counter to zero and completes the grayscale

PWM cycle (see Figure 26). When the counter reaches a count of FFFh, the counter stops counting and all outputs

turn off. Pulling OEB high before the counter reaches FFFh immediately resets the counter to zero.

OUTPUT ON TIME

The amount of time that each output is turned on is a function of the PWM clock frequency and the

programmed grayscale PWM value. The on-time of each output can be calculated using Equation 10.

T_on

+ t

on_err

(11)

T_onn is the time that OUTn turns on and sinks current









• PWMn is OUTn's programmed grayscale PWM value between 0 and 4095

• ton_err is the Output on time error defined in the Switching Characteristics Table

When using Equation 11 with very high PWMCLK frequencies and very low grayscale PWM values, the resulting

T_on time may be negative. If T_on is negative, the output does not turn on. For example, using f(PWMCLK) = 30

MHz, PWMn = 1, and the typical ton_err = 50 nS, Equation 10 calculates that OUTn turns on for -16.6 nS. This

output may not turn on under these conditions. Increasing the PWM value or reducing the PWMCLK

clock frequency ensures turn-on.

OEB

PWMCK

OUT0

(current)

OUT1

(current)

OUT15

(current)

ERR

t

pd3

t

pd3

PWM

Cycle n

PWM

Cycle n+1

t

wl1

t

wl1

t

wl1

t

h4

t

wh3

t

su4

t

pd1

t

n x t

d

t

t

pd2

4096

1

2

3

1

t

Figure 26. PWM Cycle Timing Chart