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IRMCF143TY Datasheet(PDF) 32 Page - International Rectifier |
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IRMCF143TY Datasheet(HTML) 32 Page - International Rectifier |
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32 / 35 page  IRMCF143S 32 www.irf.com © 2013 International Rectifier Submit Datasheet Feedback Month xx, year Pin Number Pin Name Internal Pull- up / down Pin Type Description 31 CMEXT -- O Unbuffered 0.6V output. Capacitor needs to be connected. 32 AREF -- O Analog reference voltage output (0.6V) 33 IFBV- -- I Op amp negative input for V phase current sensing, 0- 1.2V range 34 IFBV+ -- I Op amp positive input for V phase current sensing, 0- 1.2V range 35 IFBVO -- O Op amp output for V phase current sensing, 0-1.2V range 36 AVSS -- P Analog common 37 VDDCAP -- P Internal 1.8V output, Capacitor(s) to be connected 38 VDD1 -- P 3.3V digital power 39 VSS -- P Digital common 40 P3.1/AO2/MT3 -- I/O Discrete programmable I/O or PWM 2 digital output or MCE pin timer 3 output 41 PWMWL 58 kΩ Pull down O PWM gate drive for phase W low side, configurable either high or low true. 42 PWMVL 58 kΩ Pull down O PWM gate drive for phase V low side, configurable either high or low true 43 PWMUL 58 kΩ Pull down O PWM gate drive for phase U low side, configurable either high or low true 44 PWMWH 58 kΩ Pull down O PWM gate drive for phase W high side, configurable either high or low true 45 P3.7 -- I/O Discrete programmable I/O 46 P2.1 -- I/O Discrete programmable I/O 47 P3.6 -- I/O Discrete programmable I/O 48 PWMVH 58 kΩ Pull down O PWM gate drive for phase V high side, configurable either high or low true 49 PWMUH 58 kΩ Pull down O PWM gate drive for phase U high side, configurable either high or low true 50 P1.5 I/O Discrete programmable I/O. 51 BRAKE 70 kΩ Pull up O Brake output, configured low true at a power up 52 BRAKEGK 70 kΩ Pull up I Brake shutdown input, active low input. 53 GATEKILL 70 kΩ Pull up I PWM shutdown input, configurable digital filter, active low input. 54 P3.0/CS1 70 kΩ Pull up I/O Discrete programmable I/O or SPI Chip Select 1 55 TMS /P5.2 -- I JTAG test mode select or digital input port 56 TDO -- O JTAG test data output 57 TDI /P5.1 -- I JTAG test data input or digital input port 58 TCK -- I JTAG test clock 59 RESET -- I Reset, low true, Schmitt trigger input 60 P1.1/RXD -- I/O UART receiver input or Discrete programmable I/O 61 P1.2/TXD -- I/O UART transmitter output or Discrete programmable I/O 62 HALL-1/P3.4/T0 -- I/O Hall-1 input or discrete programmable I/O or Timer/Counter 0 input 63 HALL-2/P3.5/T1 -- I/O Hall-2 input or discrete programmable I/O or Timer/Counter 1 input 64 HALL-3/P3.3/INT1 -- I/O Hall-3 input or discrete programmable I/O or Interrupt 1 input Table 22. Pin List |
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