MAX3372EEKAT datasheet(5/26 Pages) MAXIM

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MAX3372E–MAX3379E/MAX3390E–MAX3393E

±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad

Low-Voltage Level Translators in UCSP

Maxim Integrated

Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design

and not production tested.

Note 2: For normal operation, ensure VL < (VCC + 0.3V). During power-up, VL > (VCC + 0.3V) will not damage the device.

Note 3: To ensure maximum ESD protection, place a 1µF capacitor between VCC and GND. See Applications Circuits.

Note 4: 10% to 90%

Note 5: 90% to 10%

TIMING CHARACTERISTICS (continued)

(VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA = TMIN to TMAX, unless

otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) (Notes 1, 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

+1.2V

≤ VL ≤ VCC ≤ +3.3V

I/O VCC_ Rise Time (Note 4)

tRVCC

I/O VCC_ Fall Time (Note 5)

tFVCC

I/O VL_ Rise Time (Note 4)

tRVL

I/O VL_ Fall Time (Note 5)

tFVL

I/OVL-VCC

Driving I/O VL_20

Propagation Delay

I/OVCC-VL

Driving I/O VCC_20

Channel-to-Channel Skew

tSKEW

Each translator equally loaded

Maximum Data Rate

Mbps

+2.5V

≤ VL ≤ VCC ≤ +3.3V

I/O VCC_ Rise Time (Note 4)

tRVCC

I/O VCC_ Fall Time (Note 5)

tFVCC

I/O VL_ Rise Time (Note 4)

tRVL

I/O VL_ Fall Time (Note 5)

tFVL

I/OVL-VCC

Driving I/O VL_15

Propagation Delay

I/OVCC-VL

Driving I/O VCC_15

Channel-to-Channel Skew

tSKEW

Each translator equally loaded

Maximum Data Rate

Mbps

+1.8V

≤ VL ≤ VCC ≤ +2.5V

I/O VCC_ Rise Time (Note 4)

tRVCC

I/O VCC_ Fall Time (Note 5)

tFVCC

I/O VL_ Rise Time (Note 4)

tRVL

I/O VL_ Fall Time (Note 5)

tFVL

I/OVL-VCC

Driving I/O VL_15

Propagation Delay

I/OVCC-VL

Driving I/O VCC_15

Channel-to-Channel Skew

tSKEW

Each translator equally loaded

Maximum Data Rate

Mbps

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