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E910.97 Datasheet(PDF) 7 Page - ELMOS Semiconductor AG |
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E910.97 Datasheet(HTML) 7 Page - ELMOS Semiconductor AG |
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7 / 9 page ![]() 7/9 ELMOS Semiconductor AG Data Sheet QM-No.: 25DS0091E.00 PRELIMINARY INFORMATION - JUL 28, 2011 This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. INTEGRATED CIRCUIT FOR PIR SMART SENSOR E910.97 Test Modes___________________________________________________ INPUTS OUTPUT MODE OEN ENVREG SENS ONTIME PIRIN NPIRIN REL VDD<=OEN<=VSS ENVREG SENS ONTIME PIRIN NPIRIN REL Normal Operation >VDD +0.4v ACLK SENS ONTIME PIRIN NPIRIN DOCI- DAC Data Out – Clock in ATEST2 <VSS -0.4v TCLK SENS ONTIME SDI SCAN_EN SCAN OUT Digital Test VDD<=OEN<=VSS ENVREG SENS >VDD +0.4v PIRIN NPIRIN DOCI - LPF Data Out – Clock in ATEST1 VDD<=OEN<=VSS ENVREG SENS <VSS -0.4v PIRIN NPIRIN DATA Initialize self test mode ATEST0 Table 6: Device Test nodes Analog Test Modes In ATEST1 ‘Data Out – Clock in’ (DOCI - LPF) - mode, the filter data as well as the PIN SCAN data is available as a 28 bit word on the REL output. Whenever a new filter value is generated, the REL output is switched to high level. Reading of data has to be completed in less than 30 system cycles after the REL output goes to VDD. The DOCI protocol is used to read the word. In ATEST2 ‘Data Out – Clock in’ (DOCI - DAC) - mode, the DAC data is available as a word on the REL output. The data must be read within 1 system clock. The DOCI protocol is used to read the word. Self Test Mode Self test mode is initialized by applying a voltage of less than VSS-0.4V to ONTIME. As soon as the device is switched back to normal mode (OEN=VDD), the PIR inputs are connected to a switched capacitor circuit and charged up in steps. The resulting voltages are captured like in the ATEST1 (DOCI - LPF) test mode. The data includes the voltages measured on the SENS and ONTIME inputs. Digital Test Mode The scan-path is switched with the NPIRIN input. Scan data is applied to PIRIN. ENVREG is test clock input. The levels on the PIRIN/NPIRIN inputs must be +0.5V/-0.5V (L/H). The levels on ENVREG are VDD/VSS (L/H). This test mode is only used for chip testing. Fig. 2: Pin scan and LPF DOCI data out Fig. 3: DAC DOCI data out SENS[6:0] REL 32 x C_G ONTIME[3:0] LPF FILTER[15:0] SENS[6:0] SENS[6:0] REL C_G ONTIME[3:0] DAC [5:0] SENS[6:0] |
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