RL78 datasheet(55/61 Pages) RENESAS

55 / 61 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 55 of 97

Feb 21, 2012

Note 1.

Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is

fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current.

However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors.

Note 2.

During HALT instruction execution by flash memory.

Note 3.

When high-speed on-chip oscillator and subsystem clock are stopped.

Note 4.

When high-speed system clock and subsystem clock are stopped.

Note 5.

When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When high-speed on-

chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX.

column include the leakage current.

Note 6.

When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer

is stopped. The values below the MAX. column include the leakage current.

Note 7.

Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.

High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz

VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz

Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz

Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz

Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)

Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)

Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note

Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C

Note

fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the

same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set

fCLK to fIH.

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