THS4502 datasheet(21/49 Pages) NSC

21 / 49 page

THS4502

THS4503

www.ti.com

SLOS352E

– APRIL 2002 – REVISED OCTOBER 2011

APPLICATION INFORMATION

10V, RL = 800 Ω differential, and the quiescent

current = 32mA (the maximum over 0

°C to 70°C

MAXIMUM DIE TEMPERATURE TO PREVENT

temperature range). The last entry for each package

OSCILLATION

option lists the worst case where the output voltage is

The THS4502 and THS4503 may have low level

5V DC.

oscillation when the die temperature (also called

junction temperature) exceeds +60

°C and is not

Table 1. Estimated Maximum Ambient

recommended

for

new

designs

where

the

die

Temperature Per Package Option

temperature is expected to exceed +60

°C.

PACKAGE/DEVICE

Vout

ΘJA

TA MAX

The oscillation is due to internal design and external

SOIC

28.8

°C

configuration is not expected to mitigate or reduce the

2 Vpp

28.0

°C

problem. This problem is random due to normal

4 Vpp

27.3

°C

THS4502D

process variations and normal testing cannot identify

97.5

°C/W

THS4503D

6 Vpp

26.8

°C

problem units.

8 Vpp

26.3

°C

The THS4500 and THS4501 are recommended

Worst Case =

5 DC

25.8

°C

replacement devices.

PWR Pad MSOP

41.3

°C

The

die

temperature

depends

the

power

2 Vpp

40.8

°C

dissipation and the thermal resistance of the device

4 Vpp

40.4

°C

and can be approximated with the following formula:

THS4502DGN

58.4

°C/W

THS4503DGN

6 Vpp

40.1

°C

Die Temperature = PDISS × θJA + TA

8 Vpp

39.8

°C

Where:

Worst Case =

5 DC

39.5

°C

PDISS ≈ (VS (TOTAL) × IQ) + (VS+ – VOUT) × IOUT

MSOP

-23.2

°C

Table 1 shows the estimated maximum ambient

2 Vpp

-25.3

°C

temperature (TA max) in °C for each package option

4 Vpp

-27.1

°C

THS4502DGK

of the THS4502 and THS4503 using the thermal

260

°C/W

THS4503DGK

6 Vpp

-28.6

°C

dissipation

rating

given

the

PACKAGE

DISSIPATION RATINGS table for a JEDEC standard

8 Vpp

-29.8

°C

High-K test PCB. For each case shown, VS (TOTAL) =

Worst Case =

5 DC

-31.3

°C

•

Choosing the Proper Value for the Feedback and

Gain Resistors

FULLY DIFFERENTIAL AMPLIFIERS

•

Application

Circuits

Using

Fully

Differential

Differential signaling offers a number of performance

Amplifiers

advantages in high-speed analog signal processing

•

Key Design Considerations for Interfacing to an

systems,

including

immunity

external

Analog-to-Digital Converter

common-mode noise, suppression of even-order

nonlinearities, and increased dynamic range. Fully

•

Setting the Output Common-Mode Voltage With

differential amplifiers not only serve as the primary

the VOCM Input

means of providing gain to a differential signal chain,

•

Saving Power With Power-Down Functionality

but also provide a monolithic solution for converting

•

Linearity:

Definitions,

Terminology,

Circuit

single-ended

signals

into

differential

signals

for

Techniques, and Design Tradeoffs

easier, higher performance processing. The THS4500

•

Abbreviated

Analysis

Noise

Fully

family of amplifiers contains products in Texas

Differential Amplifiers

Instruments' expanding line of high-performance fully

•

Printed-Circuit

Board

Layout

Techniques

for

differential amplifiers. Information on fully differential

Optimal Performance

amplifier fundamentals, as well as implementation

specific information, is presented in the applications

•

Power Dissipation and Thermal Considerations

section of this data sheet to provide a better

•

Power

Supply

Decoupling

Techniques

and

understanding of the operation of the THS4500 family

Recommendations

of devices, and to simplify the design process for

•

Evaluation

Fixtures,

Spice

Models,

and

designs using these amplifiers.

Applications Support

•

Additional Reference Material

Applications Section

•

Fully Differential Amplifier Terminal Functions

•

Input Common-Mode Voltage Range and the

THS4500 Family

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