CS3310 datasheet(7/18 Pages) CIRRUS

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CS3310

DS82PP3

In single device operation, volume control data is

loaded into the 16-bit shift register by holding the

CS pin low for sixteen SCLK pulses and then

latched on the rising edge of CS. The previous con-

tents of the shift-register are shifted through the

Multi-channel operation can be implemented as

shown in Figure 4 by connecting the SDATAO of

device #1 to the SDATAI pin of device #2. In this

manner multiple CS3310s can be loaded from a

single serial data line without complex addressing

schemes. Volume control data is loaded by holding

CS low for 16 x N SCLK pulses, where N is the

number of devices in the chain. The 16 bits clocked

into device #1 on SCLK pulses 1-16 are clocked

into device #2 on SCLK pulses 17-32. The

CS3310s are simultaneously updated on the rising

edge of CS following 16 x N SCLK pulses. Notice

that a 47 kohm resistor is required to terminate

SDATAI, as shown in Figure 4, due to the high im-

pedance state of SDATAO when CS is high.

Changing the Analog Output Level

Care has been taken to ensure that there are no au-

dible artifacts in the analog output signal during

volume control changes. The gain/attenuation

changes of the CS3310 occur at zero crossings to

eliminate glitches during level transitions. The zero

crossing for the left channel is the voltage potential

at the AGNDL pin; the voltage potential at the

AGNDR pin defines the right channel zero cross-

ing.

A volume control change occurs after chip select

latches the data in the volume control data register

and two zero crossings are detected. If two zero

crossings are not detected within 18 ms of the

change in CS, the new volume setting is imple-

mented. The zero crossing enable pin, ZCEN, en-

ables or disables the zero crossing detection

function as well as the 18 ms time-out circuit.

Analog Inputs and Outputs

The maximum input level is limited by the com-

mon-mode voltage capabilities of the internal op-

amp. Signals approaching the analog supply volt-

ages may be applied to the AIN pins if the internal

attenuator limits the output signal to within 1.25

volts of the analog supply rails.

The outputs are capable of driving 600

Ω loads to

within 1.25 volts of the analog supply rails and are

short circuit protected to 20 mA.

As with any adjustable gain stage the affects of a

DC offset at the input must be considered. Capaci-

tively coupling the analog inputs may be required

AUDIO

SIGNAL

AINL

AINR

SDATAI

SDATAO

AOUTL

AOUTR

SCLK

CS3310

CONTROLLER

AUDIO

SIGNAL

AINL

AINR

SDATAI

SDATAO

AOUTL

AOUTR

SCLK

CS3310

47 k

Figure 4. Daisy Chaining Diagram

Input Code

(Left or Right Channel)

Gain or Attenuation (dB)

11111111

11111110

•

11000000

•

00000010

00000001

00000000

+31.5

+31.0

•

-95.0

-95.5

Software Mute

Table 1. Input Code Definition

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