CS4954 datasheet(33/56 Pages) CIRRUS

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CS4954 CS4955

DS278PP4

transferred at a rate of up to 400 Kbits/sec in fast

mode. The number of interfaces to the bus is solely

dependent on the limiting bus capacitance of 400

pF. When 8-bit parallel interface operation is being

used, SDA and SCL can be tied directly to ground.

The I2C bus address for the CS4954/5 is program-

mable via the I2C_ADR Register (0×0F). When

I2C interface operation is being used, RD and WR

must be tied to ground. PDAT [7:0] are available to

be used for GPIO operation in I2C host interface

mode. For 3.3 V operation it is necessary to have

the appropriate level shifting for I2C signals.

8.1.2. 8-bit Parallel Interface

The CS4954/5 is equipped with a full 8-bit parallel

microprocessor write and read control port. Along

with the PDAT [7:0] pins, the control port interface

is comprised of host read (RD) and host write (WR)

active low strobes and host address enable

(ADDR), which, when low, enables unique address

internal registers which configure the CS4954/5 for

various modes of operation. The internal registers

are uniquely addressed via an address register. The

address register is accessed during a host write cy-

cle with the WR and ADDR pins set low. Host

write cycles with ADDR set high will write the 8-

bits on the PDAT [7:0] pins into the register cur-

rently selected by the address register. Likewise

read cycles occur with RD set low and ADDR set

high will return the register contents selected by the

address register. Reference the detailed electrical

timing parameter section of this data sheet for exact

host parallel interface timing characteristics and

specifications.

Trec

Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle

ADDR

PDAT[7:0]

Trd

Trpw

Trah

Trda

Trdh

Tas

Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle

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