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W210
7
1
32, 31,
29, 28
SDRAM4:7
Clock Output Disable
Low
Active
1
0
38, 37,
35, 34
SDRAM0:3
Clock Output Disable
Low
Active
1
Data Byte 4
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 5
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
1
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
48
REF1
Clock Output Disable
Low
Active
1
0
2
REF0
Clock Output Disable
Low
Active
1
Data Byte 6
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 7
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Table 5. Data Bytes 0–7 Serial Configuration Map (continued)
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1