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W210
12
Document #: 38-00846-C
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
fD
Deviation from 24 MHz
(24.004 – 24)/24
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
Cl
p
p
ip
Clock Chip
CPU
Driver
1.5V
R1
68
Z0 = 52
Ω
Length = 3”
T2
Z0 = 52
Ω
Length = 5”
T1
R8
47
CPUCLK_T
Z0 = 52
Ω
Length = 3”
T5
Z0 = 52
Ω
Length = 5”
T4
R9
47
20p
20p
CPUCLK_C
1.5V
R3
68
Figure 5. K7 Open Drain Clock Driver Test Circuit
Ordering Information
Ordering Code
Package
Name
Package Type
W210
H
48-pin SSOP (300 mils)
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