DS1844 datasheet(10/14 Pages) DALLAS

10 / 14 page

DS1844

10 of 14

101999

11.

Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired

address selections.

12.

Resistor inputs cannot go below GND by more than 0.5 volts or above VCC by more than 0.5

volts.

13.

-3dB cutoff frequency characteristics for the DS1844 depend on potentiometer total resistance:

DS1844-010; 1 MHz; DS1844-050; 200 kHz; DS1844-100; 100 kHz.

14.

See Figure 3, 5-wire timing diagram.

15.

For 5-wire control logic and VCC = 5V ±10%, maximum VIL = +0.8V. For VCC = 3.0V ±10%,VIL

= +0.6V.

16.

Absolute linearity is used to measure expected wiper voltage versus measured wiper voltage as

determined by wiper position. The DS1844 is specified to provide an absolute linearity of ± 0.5

LSB.

17.

Relative linearity is used to determine the change in wiper voltage between two adjacent wiper

positions. The DS1844 is specified to provide a relative linearity of ± 0.25 dB.

18.

When used as a rheostat or variable resistor the temperature coefficient applies: 650 ppm/°C.

When used as a voltage divider or potentiometer, the effective temperature coefficient approaches

30 ppm/°C.

19.

Maximum ICC active current is dependent on clock rates during serial port activity. Maximum

ICC active current is specified for 5 MHz clock rates, and worse case input logic levels.

20.

tSETUP is the minimum time required for the port select input, PS, to be stable before any activity

on SDA or SCL terminals.

21.

tSETUP is the minimum time required for the port select input, PS, and/or the R/ W input to be

stable before RST becomes active (or goes to a high state).

22.

See Figure 8, 5-wire timing diagram.

23.

Measured with load as shown in Figure 9.

24.

Valid for VCC = 5V only.

25.

Valid at 25

°C only.

DS1844 Datasheet(PDF) 10 Page - Dallas Semiconductor

DS1844 Datasheet(HTML) 10 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Download

Link URL