ICS85408I Datasheet

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

ICS85408BGI REVISION B JULY 2, 2009

2

©2009 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 2

nQ6, Q6

Output

Differential output pair. LVDS interface levels.

3, 4

nQ5, Q5

Output

Differential output pair. LVDS interface levels.

5, 6

nQ4, Q4

Output

Differential output pair. LVDS interface levels.

7, 8

nQ3, Q3

Output

Differential output pair. LVDS interface levels.

9, 10

nQ2, Q2

Output

Differential output pair. LVDS interface levels.

11, 12

nQ1, Q1

Output

Differential output pair. LVDS interface levels.

13, 14

nQ0, Q0

Output

Differential output pair. LVDS interface levels.

15

nCLK

Input

Pullup

Inverting differential clock input.

16

CLK

Input

Pulldown

Non-inverting differential clock input.

17, 19, 20

Power

Positive supply pins.

18, 21

GND

Power

Power supply ground.

22

OE

Input

Pullup

Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH,

the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS /

LVTTL interface levels.

23, 24

nQ7, Q7

Output

Differential output pair. LVDS interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Power Dissipation Capacitance

(per output)

4pF

Input Pullup Resistor

51

k

Ω

51

k

Ω