MA31755

2/13

1. PIN DESCRIPTIONS

POWER

BUSSES

ERROR FLAGS AND CONTROL

DEVICE AND BUFFER CONTROL

PD[0:16]

I/O

Active High

Processor data bus + parity bit (bit 16)

MD[0:16]

I/O

Active High

Memory data bus + parity bit (bit 16)

CB[0:5]

I/O

Active High

Memory check bit bus

VDD x8

Input

-

Supply - 5V nominal (all must be connected)

VSS x8

Input

-

Circuit 0V reference (all must be connected)

CERRN

Output

Active Low

Asserted low when a correctable (1 bit) error occurs (ENFLG

must be asserted high)

NCERRN

Output

Active Low

Asserted low when an uncorrectable error occurs (ENFLG

must be asserted high)

XERRN

Input

Active Low

External error feedthrough to NCERRN line.

ENCOR

Input

Active High

Enables correction of data when high. Data is passed

through uncorrected when this line is low.

ENFLG

Input

Active High

Enables the flagging of incorrect data when high. When this

line is low the two error flag lines are held inactive.

2. FUNCTIONAL DESCRIPTION

2.0 GENERAL

The EDAC is of feedthrough type with 16 data bits, 1 parity

bit and 6 check bits, giving the ability to correct all single bit

errors and detect all double bit errors. Errors in more than two

bits may result in any combination of error flags being raised

and the data may be arbitrarily modified by the correction

circuitry.

The EDAC is placed in the data bus between the processor

and the memory to be protected.

It forms the interface

between the 23-bit memory bus and the 17-bit processor bus.

Tri-statable bus transceivers with a high drive capability are

incorporated at both busses.

2.1 TESTING THE EDAC AND MEMORY SYSTEM

No specific hardware for testing is provided by the

MA31755 since this would compromise the speed

performance of the part in normal operation. However, it is

possible to fully test the EDAC function and the generation of

the error signals without this. The system should provide a

means by which the check bit memory may be dynamically

write-enabled and disabled - this may be provided by gating

write strobe on the check bit memory with a latched control bit.

By writing first with check bits enabled, then with them

disabled, suitable seed values may be constructed which have

the required pattern of bits to test each feature of the EDAC

operation. A similar approach may be taken when testing the

check bit memory.

By disabling the EDAC (asserting ENCOR low) the

processor may have direct access to the unmodified 17-bit

data from the memory. Suitable test patterns may be applied to

test each memory location as required.

CS2N

Input

Active Low

Enables device and output buffers.

CS1N

Input

Active Low

Enables device and output buffers.

CS0

Input

Active High

Enables device and output buffers.

RDWN

Input

-

High indicates a read cycle, low indicates a write cycle.