MA31755

3/13

2.2 BUS CONTROL

There are four signals which control the drive status of the EDAC external busses: RDWN, CS2N, CS1N and CS0. The

relationship to each other and to the EDAC busses is shown in Figure 2 below. The timing of these signals is shown in Figures 6

and 7.

Figure 2: Bus Control

2.3 INTERNAL OPERATION

2.3.1 Check Bit Generation

On write cycles the processor data word, PD[0:15], and the processor parity bit ,PD[16], are passed directly to the memory

data bus, MD[0:15], and the memory parity bit, MD[16].

The check bits, CB[0:5], are derived by 6 parity generators operating on sets of 8 bits of the processor data word, PD[0:15], as

shown in Figure 3 below:

Figure 3: Check Bit Generation

2.3.2 Syndrome Generation

The syndrome generation logic checks the sense of the check bits with respect to the memory data word. Six 9-input parity

checkers generate the syndrome bits, SY[0:5], according to figure 4 below:

Figure 4: Syndrome Generation

RDWN

CS2N

CS1N

CS0

Bus state

Processor

Memory

X

High

X

X

Tristate

Tristate

X

X

High

X

Tristate

Tristate

X

X

X

Low

Tristate

Tristate

High

Low

Low

High

Output

Input

Low

Low

Low

High

Input

Output

CB

Parity

PD

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

Even

X

X

X

X

X

X

X

X

1

Even

X

X

X

X

X

X

X

X

2

Odd

X

X

X

X

X

X

X

X

3

Odd

X

X

X

X

X

X

X

X

4

Even

X

X

X

X

X

X

X

X

5

Even

X

X

X

X

X

X

X

X

If there are no errors in the memory data word, MD[0:15],

or the check bits, CB[0:5], then all of the syndrome bits,

SY[0:5], will be set low.

A single bit error in the memory data word, MD[0:15], will

cause 3 syndrome bits to be set high. However, a single bit

error in the check bits, CB[0:5], will cause only 1 syndrome bit

to be set high. A two bit error in the memory data word and/or

the check bits will cause either 2, 4, 5 or 6 syndrome bits to be

set.

Three or more errors in the memory data word and/or the

check bits will cause an undefined number of syndrome bits to

be set. This will cause the operation of the device in respect of

the states of CERRN, NCERRN and data on the PD bus to be

unpredictable.

S Y

Parity

MD

CB

1 5 1 4 1 3 1 2 1 1 1 0 9876543210012345

0

Even

X

X

XXXXX

XX

1

Even

X

XXXX

X

X

X

X

2

Odd

X

X

X

X

XXXX

X

3

Odd

X

X

X

XXXXX

X

4

Even

X

XXXXX

X

X

X

5

Even

XXXXX

XX

X

X