MA9264

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Figure 12: Write Cycle

ADDRESS

(4)

WE

DATA OUT

(6)

(7)

HIGH

IMPEDANCE

DATA VALID

DATA IN

CS

CE

(5)

(8)

1.

WE must be high during all address transitions.

of the write cycle.

4. If the

CS low or CE high transition occurs simultaneously with, or after, the WE low transition, the output

remains in the high impedance state.

5. DATA OUT is in the active state, so DATA IN must not be in the opposing state.

6. DATA OUT is the write data of the current cycle, if selected.

7. DATA OUT is the read data of the next address,if selected.

8.

OE is low. (If OE is high then DATA OUT remains in the high impedance state throughout the cycle).