Micrel, Inc.

MIC4950

March 20, 2014

2

Revision 1.1

Ordering Information

Part Number

(1)

Top Mark

Temperature Range

Package

Lead Finish

MIC4950YFM

4950YFM

8-pin SOIC

Pb-Free

MIC4950YFL

MIC4950

10-pin 3mm x 4mm DFN

(2)

Pb-Free

Note:

1.

Other options are available. Contact Micrel for details.

2.

DFN is GREEN RoHS compliant package. Lead finish is NiPdAu. Mold compound is Halogen Free.

Pin Configuration

8-Pin SOIC (FM)

(Top View)

3mm x 4mm DFN (FL)

(Top View)

Pin Description

Pin Number

SOIC-8 (YFM)

Pin Number

DFN-10 (YFL)

Pin Name

Pin Function

1

1, 2, EP

PGND

Power Ground.

2

3, 8

PVIN

Power Input Voltage: Connect a 10µF ceramic capacitor between PVIN and

PGND for input decoupling. Pins 3 and 8 are internally connected in the

DFN-10 package.

3

4

AVIN

Analog Input Voltage: Connect a 1µF ceramic capacitor between AVIN and

AGND to decouple the noise from the internal reference and error comparator.

4

5

AGND

Analog Ground Input: Connect to a quiet ground plane for best operation. Do

not route power switching currents on the AGND net. Connect AGND and

PGND nets together at a single point.

5

6

FB

Feedback (Input): Connect an external divider between VOUT and AGND

(Analog Ground) to program the output voltage.

6

7

PG

Power Good (Output): Open-drain output. A pull-up resistor from this pin to a

voltage source is required to detect an output power-is-good condition.

7

9

EN

Enable (Input): Logic high enables operation of the regulator. Logic low shuts

down the device. Do not leave floating.

8

10

SW

Switch (Output): Internal power MOSFET output switches.