11

* This specification are subject to be changed without notice.

9.14.2001

EM83040B

LCD CONTROLLER

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Address 2560 bit3 (IRS) is internal resistor selected

IRS=0: internal regulator resistor is used.

IRS=1: internal regulator resistor is not used. (External resistor is used)

Address 2560 bit0~2(IR2, IR1, IR0) is selected for the V1 voltage regulator internal resistance ratio

IR2~IR0

Resistor ratio (1+Rb/Ra)

0 0 0

3.0

0 0 1

3.5

0 1 0

4.0

0 1 1

4.5

1 0 0

5.0

1 0 1

5.5

1 1 0

6.0

1 1 1

6.5

The V1 voltage can be calculated using equation A over the range where VDD < V1

≤ VOUT

V1=(1+Rb/Ra) • V

(94%~97%) depend on loading

Example: Default: IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 0), and (REG5~0)=(000000)

V1=(1+Rb/Ra) • V

When IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 1), and (REG5~0)=(100000)

V1=(1+Rb/Ra) • V

FIG. 8 show the V1 voltage measured by values of the internal resistance ratio resistor (1+Rb/Ra) for V1 voltage

adjustment and electric volume resister (REG5~REG0).

FIG. 8 The output voltage V1 is determined by function of the V1 voltage regulator ratio register (1+Rb/Ra), and

the electric volume resister (REG5~REG0).

(8) The step-up voltage circuit

Case of the double step-up, the triple step-up and Case of the quad step-up VOUT is output voltage pin the bias

voltage V1 is supported from VREG.

(a) Double step-up, (b) Triple step-up, (c) Quad step-up (d) five times step-up C1=0.47 to 1.0£gf, C2=1.0 to

4.7uf

(a) VOUT=2*VDD

(b) VOUT=3*VDD

(c) VOUT=4*VDD

(d) VOUT=5*VDD

FIG. 9

VOUT

VSS4

VSS3

CB

CA

VSS2+

VSS2-

VREG

V1

V2

V3

V4

V5

C2

C2

C1

C2

C2

C2

C1

VOUT

VSS4

VSS3

CB

CA

VSS2+

VSS2-

VREG

V1

V2

V3

V4

V5

C2

C2

C2

C2

C1

VOUT

VSS4

VSS3

CB

CA

VSS2+

VSS2-

VREG

V1

V2

V3

V4

V5

C2

C2

C2

C2

C1

VOUT

VSS4

VSS3

CB

CA

VSS2+

VSS2-

VREG

V1

V2

V3

V4

V5

C2