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PAC5220 Datasheet(PDF) 41 Page - Active-Semi, Inc |
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PAC5220 Datasheet(HTML) 41 Page - Active-Semi, Inc |
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41 / 73 page ![]() PAC5220 Power Application Controller 12.4. Electrical Characteristics Table 12-4. Gate Drivers Electrical Characteristics (VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Low-Side Gate Drivers (DRLx Pins) VOH,DRL High-level output voltage IDRLx = -50mA VP−0.5 VP−0.25 V VOL,DRL Low-level output voltage IDRLx = 50mA 0.175 0.35 V IOHPK,DRL High-level pulsed peak source current 10µs pulse -1 A IOLPK,DRL Low-level pulsed peak sink current 10µs pulse 1 A High-Side Gate Drivers (DRHx, DRBx and DRSx Pins) VDRS Level-shift driver source voltage range Repetitive, 10µs pulse -5 53 V Steady state 0 52 VDRB Bootstrap pin voltage range Repetitive, 10µs pulse 5.2 65 V Steady state 5.2 64 VBS;DRB Bootstrap supply voltage range VDRBx, relative to respective VDRSx 5.2 16 V VUVLO;DRB Bootstrap UVLO threshold VDRBx rising, relative to respective VDRSx ,Hysteresis= 1V 4.1 5.2 V IBS;DRB Bootstrap circuit supply current Gate Driver Disabled 23 35 µA Gate Driver Enabled 30 45 IOS;DRB Offset supply current Gate Driver Disabled 0.5 10 µA Gate Driver Enabled 220 300 VOH;DRH High-level output voltage IDRHx = -50mA VDRBx−0.6 VDRBx −0.25 V VOL;DRH Low-level output voltage IDRHx = 50mA VDRSx +0.175 VDRSx +0.35 V IOHPK;DRH High-level pulsed peak source current 10µs pulse -1 A IOLPK;DRH Low-level pulsed peak sink current 10µs pulse 1 A High-Side and Low-Side Gate Driver Propogation Delay tPD Propagation Delay Delay setting 00 10 ns Delay setting 01 50 ns Delay setting 10 120 ns Delay setting 11 250 ns - 41 - Rev 1.0‒February 25, 2014 |
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