| Electronic Components Datasheet Search |
|
ADC12DC080 Datasheet(PDF) 4 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADC12DC080 Datasheet(HTML) 4 Page - Texas Instruments |
|
4 / 27 page ![]() DRGND VDR VA DRGND AGND VA ADC12DC080 SNAS405B – SEPTEMBER 2007 – REVISED NOVEMBER 2008 www.ti.com Pin No. Symbol Equivalent Circuit Description The clock input pin. 18 CLK The analog inputs are sampled on the rising edge of the clock input. This is a two-state input controlling Power Down. 57 PD_A PD = VA, Power Down is enabled and power dissipation is reduced. 20 PD_B PD = AGND, Normal operation. Digital data output pins that make up the 12-bit conversion result for 42-49, DA0-DA7, Channel A. DA0 (pin 42) is the LSB, while DA11 (pin 55) is the MSB 52-55 DA8-DA11 of the output word. Output levels are CMOS compatible. Digital data output pins that make up the 12-bit conversion result for 23-24, DB0-DB1, Channel B. DB0 (pin 23) is the LSB, while DB11 (pin 36) is the MSB 27-36 DB3-DB11 of the output word. Output levels are CMOS compatible. Data Ready Strobe. The data output transition is synchronized with 39 DRDY the falling edge of this signal. This signal switches at the same frequency as the CLK input. ANALOG POWER Positive analog supply pins. These pins should be connected to a 8, 16, 17, 58, VA quiet source and be bypassed to AGND with 0.1 µF capacitors 60 located close to the power pins. The ground return for the analog supply. 1, 4, 12, 15, AGND The exposed pad on back of package must be soldered to ground Exposed Pad plane to ensure rated performance. DIGITAL POWER Positive driver supply pin for the output drivers. This pin should be 26, 38,50 VDR connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. The ground return for the digital output driver supply. This pins 25, 37, 51 DRGND should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: ADC12DC080 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |