COP8SCR9 datasheet(21/105 Pages) TI1

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COP8SBR9, COP8SCR9, COP8SDR9

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SNOS537I – JUNE 2000 – REVISED MARCH 2013

Functional Description

The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the

program memory (Flash) is separate from the data store memory (RAM). Both Program Memory and Data

Memory have their own separate addressing space with separate address buses. The architecture, though

based on the Harvard architecture, permits transfer of data from Flash Memory to RAM.

5.1

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tC) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or

decremented.

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to

7F) into 256 data segments of 128 bytes each.

SP is the 8-bit stack pointer, which points to the subroutine/interrupt stack (in RAM). With reset the SP is

initialized to RAM address 06F Hex. The SP is decremented as items are pushed onto the stack. SP

points to the next available location on the stack.

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program

Counter (PC).

5.2

PROGRAM MEMORY

The program memory consists of 32,768 bytes of Flash Memory. These bytes may hold program

instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and

interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter

(PC). All interrupts in the device vector to program memory location 00FF Hex. The program memory

reads 00 Hex in the erased state. Program execution starts at location 0 after RESET.

If a Return instruction is executed when the SP contains 6F (hex), instruction execution will continue from

Program Memory location 7FFF (hex). If location 7FFF is accessed by an instruction fetch, the Flash

Memory will return a value of 00. This is the opcode for the INTR instruction and will cause a Software

Trap.

For the purpose of erasing and rewriting the Flash Memory, it is organized in pages of 128 bytes.

5.3

DATA MEMORY

The data memory address space includes the on-chip RAM and data registers, the I/O registers

(Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the

various registers, and counters associated with the timers and the USART (with the exception of the IDLE

timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

The data memory consists of 1024 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at

addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested

with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, B

and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively, with the

other registers being available for general usage.

Functional Description

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