COP8SCR9 datasheet(79/105 Pages) TI1

79 / 105 page

COP8SBR9, COP8SCR9, COP8SDR9

www.ti.com

SNOS537I – JUNE 2000 – REVISED MARCH 2013

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When using any of the ISP functions in Boot ROM, the ISP routines will service the WATCHDOG

within the selected upper window. Upon return to flash memory, the WATCHDOG is serviced, the

lower window is enabled, and the user can service the WATCHDOG anytime following exit from Boot

ROM, but must service it within the selected upper window to avoid a WATCHDOG error.

5.15.4 DETECTION OF ILLEGAL CONDITIONS

The device can detect various illegal conditions resulting from coding errors, transient noise, power supply

voltage drops, runaway programs, etc.

Reading of unprogrammed ROM gets zeros. The opcode for software interrupt is 00. If the program

fetches instructions from unprogrammed ROM, this will force a software interrupt, thus signaling that an

illegal condition has occurred.

The subroutine stack grows down for each call (jump to subroutine), interrupt, or PUSH, and grows up for

each return or POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if

there are more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are

undefined RAM). Undefined RAM from addresses 070 to 07F (Segment 0), and all other segments (i.e.,

Segments 4... etc.) is read as all 1's, which in turn will cause the program to return to address 7FFF Hex.

The Option Register is located at this location and, when accessed by an instruction fetch, will respond

with an INTR instruction (all 0's) to generate a software interrupt, signalling an illegal condition on overpop

of the stack.

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined Program Memory

2. Over “POP”ing the stack by having more returns than calls.

When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery

procedure before restarting (this recovery program is probably similar to that following reset, but might not

contain the same program initialization procedures). The recovery program should reset the software

interrupt pending bit using the RPND instruction.

5.16 MICROWIRE/PLUS

MICROWIRE/PLUS

serial

SPI

compatible

synchronous

communications

interface.

The

MICROWIRE/PLUS capability enables the device to interface with MICROWIRE/PLUS or SPI peripherals

(i.e. A/D converters, display drivers, EEPROMs etc.) and with other microcontrollers which support the

MICROWIRE/PLUS or SPI interface. It consists of an 8-bit serial shift register (SIO) with serial data input

(SI), serial data output (SO) and serial shift clock (SK). Figure 5-23 shows a block diagram of the

MICROWIRE/PLUS logic.

The shift clock can be selected from either an internal source or an external source. Operating the

MICROWIRE/PLUS arrangement with the internal clock source is called the Master mode of operation.

Similarly, operating the MICROWIRE/PLUS arrangement with an external shift clock is called the Slave

mode of operation.

The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the

MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock

rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table 5-22 details the different clock

rates that may be selected.

Table 5-22. MICROWIRE/PLUS Master Mode Clock Select

SL1

SL0

SK Period(1)

2 × tC

4 × tC

8 × tC

(1)

Where tC is the instruction cycle clock

Functional Description

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