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IR2111STR Datasheet(PDF) 3 Page - International Rectifier |
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IR2111STR Datasheet(HTML) 3 Page - International Rectifier |
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3 / 15 page  IR2111(S)&(PbF) www.irf.com 3 Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic “1” input voltage for HO & logic “0” for LO 6.4 — — VCC = 10V 9.5 — — VCC = 15V 12.6 — — VCC = 20V VIL Logic “0” input voltage for HO & logic “1” for LO — — 3.8 VCC = 10V — — 6.0 VCC = 15V — — 8.3 VCC = 20V VOH High level output voltage, VBIAS - VO — — 100 IO = 0A VOL Low level output voltage, VO — — 100 IO = 0A ILK Offset supply leakage current — — 50 VB = VS = 600V IQBS Quiescent VBS supply current — 50 100 VIN = 0V or VCC IQCC Quiescent VCC supply current — 70 180 VIN = 0V or VCC IIN+ Logic “1” input bias current — 30 50 VIN = VCC IIN- Logic “0” input bias current — — 1.0 VIN = 0V VBSUV+ VBS supply undervoltage positive going threshold 7.6 8.6 9.6 VBSUV- VBS supply undervoltage negative going threshold 7.2 8.2 9.2 VCCUV+ VCC supply undervoltage positive going threshold 7.6 8.6 9.6 VCCUV- VCC supply undervoltage negative going threshold 7.2 8.2 9.2 IO+ Output high short circuit pulsed current 200 250 — VO = 0V, VIN = VCC PW ≤ 10 µs IO- Output low short circuit pulsed current 420 500 — VO = 15V, VIN = 0V PW ≤ 10 µs Static Electrical Characteristics VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. mV mA V V µA Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay 550 750 950 VS = 0V toff Turn-off propagation delay — 150 180 VS = 600V tr Turn-on rise time — 80 130 tf Turn-off fall time — 40 65 DT Deadtime, LS turn-off to HS turn-on & 480 650 820 HS turn-off to LS turn-on MT Delay matching, HS & LS turn-on/off — 30 — Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in figure 3. ns |
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