Electronic Components Datasheet Search
  English  ▼

X  

WM1811A Datasheet(PDF) 152 Page - Wolfson Microelectronics plc

Part # WM1811A
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 152 Page - Wolfson Microelectronics plc

Back Button WM1811A Datasheet HTML 148Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 149Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 150Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 151Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 152Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 153Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 154Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 155Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 156Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 152 / 328 page
background image
WM1811A
Production Data
w
PD, November 2013, Rev 4.1
152
DIGITAL AUDIO INTERFACE
The WM1811A provides digital audio interfaces for inputting DAC data and outputting ADCor Digital
Microphone data. Flexible routing options also allow digital audio to be switched or mixed between
interfaces without involving any DAC or ADC.
The WM1811A provides two full audio interfaces, AIF1 and AIF2. A third interface, AIF3, supports
Mono PCM digital audio paths to/from the AIF2 DSP functions. AIF3 can also be configured using
multiplexers to provide alternate connections to AIF1 or AIF2.
The digital audio interfaces provide flexible connectivity with multiple processors (eg. Applications
processor, Baseband processor and Wireless transceiver). A typical configuration is illustrated in
Figure 44.
Figure 44 Typical AIF Connections
In the general case, the digital audio interface uses four pins:
ADCDAT: ADC data output
DACDAT: DAC data input
LRCLK: Left/Right data alignment clock
BCLK: Bit clock, for synchronisation
In master interface mode, the clock signals BCLK and LRCLK are outputs from the WM1811A. In
slave mode, these signals are inputs, as illustrated below.
As an option (AIF1 only), a GPIO pin can be configured as the Left/Right clock for the ADC. In this
case, the LRCLK pin is dedicated to the DAC, allowing the ADC and DAC to be clocked
independently.
Four different audio data formats are supported each digital audio interface:
Left justified
Right justified
I
2S
DSP mode



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com