WM1811A datasheet(148/328 Pages) WOLFSON

148 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

148

INTERRUPTS

The Interrupt Controller has multiple inputs. These include the GPIO input pins, the FLL Lock circuits,

SRC Lock circuit, Microphone activity detection, Over-temperature indication and Digital FIFO error

detection. Any combination of these inputs can be used to trigger an Interrupt Request (IRQ) event.

There is an Interrupt register field associated with each of the interrupt inputs. These fields are

asserted whenever a logic edge is detected on the respective input. Some inputs are triggered on

rising edges only; some are triggered on both edges, as noted in Table 84. The Interrupt register fields

are held in Registers R1840 and R1841. The Interrupt flags can be polled at any time from these

registers, or else in response to the Interrupt Request (IRQ) output being signalled via a GPIO pin.

All of the Interrupts are edge-triggered, as noted above. Many of these are triggered on both the rising

and falling edges and, therefore, the Interrupt registers cannot indicate which edge has been

detected. The “Raw Status” fields in Register R1842 provide readback of the current value of selected

inputs to the Interrupt Controller. Note that the logic levels of any GPIO inputs can be read using the

GPn_LVL registers, as described in Table 79.

Individual mask bits can select or deselect different functions from the Interrupt controller. These are

listed within the Interrupt Status Mask registers, as described in Table 84. Note that the Interrupt

Request (IRQ) output to be asserted.

The Interrupt Request (IRQ) output represents the logical ‘OR’ of all the unmasked interrupts. The

Interrupt register fields are latching fields and, once they are set, they are not reset until a ‘1’ is written

to the respective register bit(s). The Interrupt Request (IRQ) output is not reset until each of the

unmasked interrupts has been reset.

De-bouncing of the GPIO inputs can be enabled using the register bits described in Table 79. De-

bouncing is also available on the Temperature Warning and Temperature Shutdown inputs to the

Interrupt Controller, in order to avoid false detections - see Table 84 for the associated registers.

The Interrupt Request (IRQ) output can be globally masked by setting the IM_IRQ register. Under

default conditions, the Interrupt Request (IRQ) is not masked.

The Interrupt Request (IRQ) flag may be output on a GPIO pin - see “General Purpose Input/Output”.

The WM1811A Interrupt Controller circuit is illustrated in Figure 43. (Note that not all interrupt inputs

are shown.) The associated control fields are described in Table 84.

Figure 43 Interrupt Controller

WM1811A Datasheet(PDF) 148 Page - Wolfson Microelectronics plc