WM1811A datasheet(145/328 Pages) WOLFSON

145 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

145

DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION

Signal activity detection is provided on each of the Dynamic Range Controllers (DRCs). These may be

configured to indicate when a signal is present on the respective signal path. The signal activity status

signals may be used to control other events if required. See “Digital Core Architecture” for more

details of the DRCs and the available digital signal paths.

When a DRC is enabled, as described in “Dynamic Range Control (DRC)”, then signal activity

detection can be enabled by setting the respective [DRC]_SIG_DET register bit. The applicable

threshold can be defined either as a Peak level (Crest Factor) or an RMS level, depending on the

[DRC]_SIG_DET_MODE register bit. When Peak level is selected, the threshold is determined by

[DRC]_SIG_DET_PK, which defines the applicable Crest Factor (Peak to RMS ratio) threshold. If

RMS level is selected, then the threshold is set using [DRC]_SIG_DET_RMS. These register fields

are set independently for each of the three Dynamic Range Controllers, as described in Table 82.

When the DRC is enabled in any of the ADC (digital record) paths, the associated High Pass Filter

(HPF) must be enabled also; this ensures that DC offsets are removed prior to the DRC processing.

The output path HPF control registers are described in Table 37 (for AIF1 output paths) and Table 45

(for AIF2 output paths). These are described in the “Digital Volume and Filter Control” section.

The DRC Signal Detect signals may be output directly on any GPIO pin by setting the respective

GPIO registers as described in “GPIO Control”.

The DRC Signal Detect signals are inputs to the Interrupt control circuit. An interrupt event is triggered

on the rising edge of the DRC Signal Detect signals. The associated interrupt bits are latched once

set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details

of the Interrupt event handling.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1088

(0440h)

AIF1 DRC1

(1)

15:11

AIF1DRC1_SIG_

DET_RMS [4:0]

00000

AIF1 DRC Signal Detect RMS

Threshold.

This is the RMS signal level for signal

detect to be indicated when

AIF1DRC1_SIG_DET_MODE=1.

00000 = -30dB

00001 = -31.5dB

…. (1.5dB steps)

11110 = -75dB

11111 = -76.5dB

10:9

AIF1DRC1_SIG_

DET_PK [1:0]

AIF1 DRC Signal Detect Peak

Threshold.

This is the Peak/RMS ratio, or Crest

Factor, level for signal detect to be

indicated when

AIF1DRC1_SIG_DET_MODE=0.

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

AIF1DRC1_SIG_

DET_MODE

AIF1 DRC Signal Detect Mode

0 = Peakthreshold mode

1 = RMSthreshold mode

AIF1DRC1_SIG_

DET

AIF1 DRC Signal Detect Enable

0 = Disabled

1 = Enabled

WM1811A Datasheet(PDF) 145 Page - Wolfson Microelectronics plc

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