WM1811A datasheet(206/328 Pages) WOLFSON

206 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

206

LDO REGULATORS

The WM1811A provides two integrated Low Drop-Out Regulators (LDOs). These are provided to

generate the appropriate power supplies for internal circuits, simplifying and reducing the

requirements for external supplies and associated components. A reference circuit powered by

AVDD2 ensures the accuracy of the LDO regulator voltage settings.

Note that the integrated LDOs are only intended for generating the AVDD1 and DCVDD supply rails

for the WM1811A; they are not suitable for powering any additional or external loads.

LDO1 is intended for generating AVDD1 - the primary analogue power domain of the WM1811A.

LDO1 is powered by LDO1VDD and is enabled when a logic ‘1’ is applied to the LDO1ENA pin. The

logic level is determined with respect to the DBVDD1 voltage domain. The LDO1 start-up time is

dependent on the external AVDD1 and VREFC capacitors; the start-up time is noted in the “Electrical

Characteristics” section for the recommended external component conditions.

When LDO1 is enabled, the output voltage is controlled by the LDO1_VSEL register field. Note that

the LDO1 voltage difference LDO1VDD - AVDD1 must be higher than the LDO1 Drop-Out voltage

(see “Electrical Characteristics”).

When LDO1 is disabled(by applying a logic ‘0’ to the LDO1ENA pin), the output can be left floating or

can be actively discharged, depending on the LDO1_DISCH control bit.

It is possible to supply AVDD1 from an external supply. If AVDD1 is supplied externally, then LDO1

should be disabled, and the LDO1 output left floating (LDO1DISCH = 0). Note that the LDO1VDD

voltage must be greater than or equal to AVDD1; this ensures that there is no leakage path through

the LDO for the external supply.

Note that the WM1811A can operate with AVDD1 tied to 0V; power consumption may be reduced, but

the analogue audio functions will not be supported.

LDO2 is intended for generating the DCVDD power domain which supplies the digital core functions

on the WM1811A. LDO2 is powered by DBVDD1 and is enabled when a logic ‘1’ is applied to the

LDO2ENA pin. The logic level is determined with respect to the DBVDD1 voltage domain.The LDO2

start-up time is dependent on the external DCVDD and VREFC capacitors; the start-up time is noted

in the “Electrical Characteristics” section for the recommended external component conditions.

When LDO2 is enabled, the output voltage is controlled by the LDO2_VSEL register field.

When LDO2 is disabled (by applying a logic ‘0’ to the LDO2ENA pin), the output can be left floating or

can be actively discharged, depending on the LDO2_DISCH control bit.

It is possible to supply DCVDD from an external supply. If DCVDD is supplied externally, the

LDO2ENA and LDO2DISCH bits should be set to 0. Note that the DBVDD1 voltage must be greater

than or equal to DCVDD; this ensures that there is no leakage path through the LDO for the external

supply.

An internal pull-down resistor is enabled by default on the LDO1ENA and LDO2ENA pins. These pull-

down resistors can be configured using the register bits described in Table 127.

Decoupling capacitors should be connected to the voltage reference pin, VREFC, and also to the LDO

outputs, AVDD1 and DCVDD. See “Applications Information” for further details.

The LDO Regulator connections and controls are illustrated in Figure 79. The register controls are

defined in Table 127.

WM1811A Datasheet(PDF) 206 Page - Wolfson Microelectronics plc

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