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WM1811A Datasheet(PDF) 218 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 218 Page - Wolfson Microelectronics plc |
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218 / 328 page  WM1811A Production Data w PD, November 2013, Rev 4.1 218 REGISTER MAP The WM1811A control registers are listed below. Note that only the register addresses described here should be accessed; writing to other addresses may result in undefined behaviour. Register bits that are not documented should not be changed from the default values. REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R0 (0h) Software Reset SW_RESET [15:0] 0000h R1 (1h) Power Management (1) 0 0 SPKO UTR_ ENA SPKO UTL_E NA HPOU T2_EN A 0 HPOU T1L_E NA HPOU T1R_E NA 0 0 MICB2 _ENA MICB1 _ENA 0 VMID_SEL [1:0] BIAS_ ENA 0000h R2 (2h) Power Management (2) 0 TSHU T_ENA TSHU T_OP DIS 0 OPCL K_EN A 0 MIXIN L_ENA MIXIN R_EN A IN2L_ ENA IN1L_ ENA IN2R_ ENA IN1R_ ENA 0 0 0 0 6000h R3 (3h) Power Management (3) 0 0 LINEO UT1N_ ENA LINEO UT1P_ ENA LINEO UT2N_ ENA LINEO UT2P_ ENA SPKR VOL_E NA SPKLV OL_E NA MIXO UTLV OL_E NA MIXO UTRV OL_E NA MIXO UTL_E NA MIXO UTR_ ENA 0 0 0 0 0000h R4 (4h) Power Management (4) 0 0 AIF2A DCL_E NA AIF2A DCR_ ENA 0 0 AIF1A DC1L_ ENA AIF1A DC1R_ ENA 0 0 0 0 DMIC1 L_ENA DMIC1 R_EN A ADCL_ ENA ADCR _ENA 0000h R5 (5h) Power Management (5) 0 0 AIF2D ACL_E NA AIF2D ACR_ ENA 0 0 AIF1D AC1L_ ENA AIF1D AC1R_ ENA 0 0 0 0 0 0 DAC1L _ENA DAC1 R_EN A 0000h R6 (6h) Power Management (6) 0 0 0 0 0 AIF3ADC_SRC [1:0] AIF2DAC_SRC [1:0] 0 AIF3_ TRI AIF3_ADCDAT _SRC [1:0] AIF2_ ADCD AT_SR C AIF2_ DACD AT_SR C AIF1_ DACD AT_SR C 0000h R21 (15h) Input Mixer (1) 0 0 0 0 0 0 0 IN1RP _MIXI NR_B OOST IN1LP _MIXI NL_B OOST INPUT S_CLA MP 0 0 0 0 0 0 0000h R24 (18h) Left Line Input 1&2 Volume 0 0 0 0 0 0 0 IN1_V U IN1L_ MUTE IN1L_ ZC 0 IN1L_VOL [4:0] 008Bh R25 (19h) Left Line Input 3&4 Volume 0 0 0 0 0 0 0 IN2_V U IN2L_ MUTE IN2L_ ZC 0 IN2L_VOL [4:0] 008Bh R26 (1Ah) Right Line Input 1&2 Volume 0 0 0 0 0 0 0 IN1_V U IN1R_ MUTE IN1R_ ZC 0 IN1R_VOL [4:0] 008Bh R27 (1Bh) Right Line Input 3&4 Volume 0 0 0 0 0 0 0 IN2_V U IN2R_ MUTE IN2R_ ZC 0 IN2R_VOL [4:0] 008Bh R28 (1Ch) Left Output Volume 0 0 0 0 0 0 0 HPOU T1_VU HPOU T1L_Z C HPOU T1L_M UTE_ N HPOUT1L_VOL [5:0] 006Dh R29 (1Dh) Right Output Volume 0 0 0 0 0 0 0 HPOU T1_VU HPOU T1R_Z C HPOU T1R_ MUTE _N HPOUT1R_VOL [5:0] 006Dh R30 (1Eh) Line Outputs Volume 0 0 0 0 0 0 0 0 0 LINEO UT1N_ MUTE LINEO UT1P_ MUTE LINEO UT1_V OL 0 LINEO UT2N_ MUTE LINEO UT2P_ MUTE LINEO UT2_V OL 0066h R31 (1Fh) HPOUT2 Volume 0 0 0 0 0 0 0 0 0 0 HPOU T2_M UTE HPOU T2_VO L 0 0 0 0 0020h R32 (20h) Left OPGA Volume 0 0 0 0 0 0 0 MIXO UT_V U MIXO UTL_Z C MIXO UTL_ MUTE _N MIXOUTL_VOL [5:0] 0079h |
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