WM1811A datasheet(215/328 Pages) WOLFSON

215 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

215

POWER ON RESET

The WM1811A includes a Power-On Reset (POR) circuit, which isused to reset the digital logic into a

default state after power up. The POR circuit derives its output from AVDD2 and DCVDD. The internal

POR

¯¯¯ signal is asserted low when AVDD2 and DCVDD are below minimum thresholds.

The specific behaviour of the circuit will vary, depending on relative timing of the supply voltages.

Typical scenarios are illustrated in Figure 80 and Figure 81.

Figure 80 Power On Reset Timing – AVDD2 enabled/disabled first

Figure 81 Power On Reset Timing - DCVDD enabled/disabled first

The POR

¯¯¯ signal is undefined until AVDD2 has exceeded the minimum threshold, Vpora. Once this

threshold has been exceeded, POR

¯¯¯ is asserted low and the chip is held in reset. In this condition, all

writes to the control interface are ignored. Once AVDD2 and DCVDD have reached their respective

power on thresholds, POR

¯¯¯ is released high, all registers are in their default state, and writes to the

control interface may take place.

Note that a power-on reset period, TPOR, applies afterAVDD2 and DCVDD have reached their

respective power on thresholds. This specification is guaranteed by design rather than test.

On power down, POR

¯¯¯ is asserted low when either AVDD2 or DCVDD falls below their respective

power-down thresholds.

WM1811A Datasheet(PDF) 215 Page - Wolfson Microelectronics plc