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WM1811A Datasheet(PDF) 213 Page - Wolfson Microelectronics plc

Part # WM1811A
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 213 Page - Wolfson Microelectronics plc

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Production Data
WM1811A
w
PD, November 2013, Rev 4.1
213
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
1 = Enabled
R76 (004Ch)
Charge Pump
(1)
15
CP_ENA
0
Enable charge-pump digits
0 = Disable
1 = Enable
R84 (0054h)
DC Servo (1)
1
DCS_ENA_CHAN
_1
0
DC Servo enable for HPOUT1R
0 = Disabled
1 = Enabled
0
DCS_ENA_CHAN
_0
0
DC Servo enable for HPOUT1L
0 = Disabled
1 = Enabled
R512 (0200h)
AIF 1 Clocking
(1)
0
AIF1CLK_ENA
0
AIF1CLK Enable
0 = Disabled
1 = Enabled
R516 (0204h)
AIF 2 Clocking
(1)
0
AIF2CLK_ENA
0
AIF2CLK Enable
0 = Disabled
1 = Enabled
R520 (0208h)
Clocking (1)
4
TOCLK_ENA
0
Slow Clock (TOCLK) Enable
0 = Disabled
1 = Enabled
This clock is required for zero-cross
timeout.
3
AIF1DSPCLK_EN
A
0
AIF1 Processing Clock Enable
0 = Disabled
1 = Enabled
2
AIF2DSPCLK_EN
A
0
AIF2 Processing Clock Enable
0 = Disabled
1 = Enabled
1
SYSDSPCLK_EN
A
0
Digital Mixing Processor Clock Enable
0 = Disabled
1 = Enabled
R544 (0220h)
FLL1 Control
(1)
0
FLL1_ENA
0
FLL1 Enable
0 = Disabled
1 = Enabled
This should be set as the final step of
the FLL1 enable sequence, ie. after the
other FLL registers have been
configured.
R576 (0240h)
FLL2 Control
(1)
0
FLL2_ENA
0
FLL2 Enable
0 = Disabled
1 = Enabled
This should be set as the final step of
the FLL2 enable sequence, ie. after the
other FLL registers have been
configured.
Table 130 Power Management



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