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AT90PWM2 Datasheet(PDF) 212 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 212 Page - ATMEL Corporation |
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212 / 365 page ![]() 212 4317K–AVR–03/2013 AT90PWM2/3/2B/3B 19. EUSART (Extended USART) The Extended Universal Synchronous and Asynchronous serial Receiver and Transmitter (EUSART) provides functionnal extensions to the USART. 19.1 Features • Independant bit number configuration for transmit and receive • Supports Serial Frames with 5, 6, 7, 8, 9 or 13, 14, 15, 16, 17 Data Bits and 1 or 2 Stop Bits • Biphase Manchester encoder/decoder (for DALI Communications) • Manchester framing error detection • Bit ordering (MSB first or LSB first) 19.2 Overview A simplified block diagram of the EUSART Transmitter is shown in Figure 19-1. CPU accessible I/O Registers and I/O pins are shown in bold. Figure 19-1. EUSART Block Diagram The EUSART is activated with the EUSART bit of EUCSRB register. Until this bit is not set, the USART will behave as standard USART, all the functionnalities of the EUSART are not accessible. PARITY GENERATOR UBRR[H:L] UDR (Transmit) EUDR (Transmit) UDR (Receive) EUDR (Receive) UCSRA UCSRB UCSRC EUCSRA EUCSRB EUCSRC BAUD RATE GENERATOR TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER RxD TxD PIN CONTROL PIN CONTROL XCK DATA RECOVERY CLOCK RECOVERY PIN CONTROL TX CONTROL RX CONTROL PARITY CHECKER MANCHESTER ENCODER CLKio SYNC LOGIC Clock Generator Transmitter Receiver MANCHESTER DECODER |
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