AT90PWM2 datasheet(215/365 Pages) ATMEL

215 / 365 page

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4317K–AVR–03/2013

AT90PWM2/3/2B/3B

19.3.3.2

Manchester decoder

When configured in Manchester mode, the EUSART receiver is able to receive serial frame

using a 17-bit shift register, an edge detector and several data/control registers. The Manchester

decoder receives a frame from the RxD pin of the EUSART interface and loads the received

data in the EUSART data register (UDR and EUDR).

The bit order of the data bits in the frame is configurable to handle MSB or LSB first.

The polarity of the bi-phase start is not configurable. The start bit a logical ‘1’ (rising edge at bit

center).

The polarity of the stop bits is not configurable, the interface allows to read the 2 stops bits value

by software.

The Manchester decoder is enable when the EUSART is configured in Manchester mode and

the RXEN of USCRB set (global USART receive enable).

The number of data bits to be received can be configured with the URxS bits of EUCSRA

The Manchester decoder provides a special mode where 16 or 17 data bits can be received. In

this mode the Manchester decoder can automatically detects if the seventeenth bit is Manches-

ter encoded or not (seventeenth data bit or first stop bit). If the receiver detects a valid data bit

(Manchester transition) during the seventeenth bit time of the frame, the receiver will process the

frame as a 17-bit frame lenght and set the F1617 bit of EUCSRC register.

In Manchester mode, the clock used for sampling the EUSART input signal is programmed by

the baudrate generator.

The edge detector of the Manchester decoder is based upon a 16 bits up/down counter which

maximum value can be configured through the MUBRRH and MUBRRL registers.

The maximum counter value is given by the following formula:

MUBRR[H:L]=F

CLKIO / (baud rate frequency)

MBURR[H:L] is used to calibrate the detect window of the start bit and to detect time overflow of

the other bits.

19.3.4

Double Speed Operation (U2X)

Double Speed Operation is controlled by U2X bit in UCSRA. See “Double Speed Operation

(U2X)” on page 188.

This mode of operation is not allowed in manchester bit coding.

Each ‘bit time’ in the Manchester serial frame is divided into two phases (See Figure 19-4). The

counter counts during the first phase and counts down during the second one. When the data bit

transition is detected, the counter memorises the N1 counter value and start counting down.

When the counter reaches the zero value, it starts counting up again and the N1/2 value allows

to open the next detection window. This detection window defines the time zone where the next

data bit edge is sampled.

AT90PWM2 Datasheet(PDF) 215 Page - ATMEL Corporation

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