AT90PWM2 datasheet(213/365 Pages) ATMEL

213 / 365 page

213

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

The EUSART supports more serial frame formats than the standard USART interface:

•

Asynchonous frames

–

Standard bit level encoded

–

Manchester bit encoded

•

Synchronous frames

–

In this mode only the Standard bit level encoded is available

19.3

Serial Frames

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking.

19.3.1

Frame Formats

The EUSART allows to receive and transmit serial frame with the following format:

•

1 start bit

•

5, 6, 7, 8, 9, 13, 14,15,16,17 data bits

•

data bits and start bit level encoded or Manchester encoded

•

data transmition MSB or LSB first (bit ordering)

•

no, even or odd parity bit

•

1 or 2 stop bits:

–

Stop bits insertion for transmition

–

Stop bits value read access in reception

The frame format used by the EUSART can be configured th rough the fo llowing

USART/EUSART registers:

•

UTxS3:0 and URxS3:0 (EUCSRA of EUSART register) select the number of data bits per

frame

•

UPM1:0 bits enable and set the type of parity bit (when configured in Manchester mode, the

parity should be fixed to none).

USBS (UCSRC register of USART) and EUSBS (EUCSRB register of EUSART) select the num-

ber of stop bits to be processed respectively by the transmiter and the receiver. The receiver

stores the two stop bit values when configured in Manchester mode. When configured in level

encoded mode, the second stop bit is ignored (behavior similar as the USART).

19.3.2

Parity Bit Calculation

The parity bit behavior is similar to the USART mode, except for the Manchester encoded mode,

where no parity bit can be inserted or detected (should be configured to none with the

UPM1:0

bits. The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used,

the result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

even

Parity bit using even parity

odd

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

even

–



odd





–







AT90PWM2 Datasheet(PDF) 213 Page - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 213 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL