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GMS34004 Datasheet(PDF) 22 Page - Hynix Semiconductor |
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GMS34004 Datasheet(HTML) 22 Page - Hynix Semiconductor |
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22 / 105 page  2 - 5 State Counter (SC) A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequencially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Fetch cycle N Execute cycle N-1 Execute cycle N Fetch cycle N-1 Machine Cycle Machine Cycle Phase¥° Phase¥± Phase¥² Fig. 2-3 Fundamental timing chart Chapter 2. Architecture |
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