GMS81608 datasheet(49/79 Pages) HYNIX

49 / 79 page

POWER FAIL PROCESSOR

The GMS81604/08 have on-chip power fail detection

circuitry to immunize against power noise. A configu-

ration register, PFDR, can enable (if clear/pro-

grammed) or disable (if set) the Power-fail Detect

circuitry. If VDD falls below 3.0~4.0V range for longer

than 100 ns, the Power fail situation may reset MCU

according to PFR bit of PFDR.

Caution:

Power fail processor function is not available on

3V operation, because this function will detect

power fail all the time.

As below PFDR register is not implemented on the

in-circuit emulator, user can not experiment with it.

Therefore, after final development of user program,

this function may be experimented.

R/W

MSB

PFR

PFD

PFS

PFDR

ADDRESS: EDH

RESET VALUE: -----100

Power Fail Status

0: Normal operate

1: This bit force to "1" when Power fail was

detected.

Reserved

Operation Mode

0: Normal operation regardless of power fail.

1: MCU will be reset during power fail.

Disable flag

0: Power fail detection enable

1: Power fail detection disable

R/W

LSB

Figure 41. PFDR: Power Fail Detector Register

RESET VECTOR

PFS = 1 ?

RAM CLEAR

INITIALIZE RAM DATA

YES

FUNCTION

EXECUTION

INITIALIZE ALL PORTS

INITIALIZE REGISTERS

Skip the initial routine.

PFS = 0

Figure 42. Example S/W of Reset flow by Power Fail

LG Semicon

GMS81604/08

GMS81608 Datasheet(PDF) 49 Page - Hynix Semiconductor

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