HMS91C8032 datasheet(89/157 Pages) HYNIX

89 / 157 page

HMS91C8032/97C8032

NOV., 2001 Ver 1.02

2. The current (polling) cycle is not the final cycle in the execu-

tion of the instruction in progress.

3. The RETI instruction in progress or any write to the IEs or IPs

registers.

Any of these three conditions will block the generation of the

LCALL to the interrupt service routine, Condition 2 ensures that

the instruction in progress will be completed before vectoring to

any service routine. Condition 3 ensures that if the instruction in

progress is RETI or any access to IEs or IPs, then at least one

more instruction will be executed before any interrupt is vectored

to.

The polling cycle is repeated with each machine cycle, and the

values polled are the values that were present at S5P2 of the pre-

vious machine cycle. Note that if an interrupt flag is active but not

being responded to for one of the above conditions, and is not still

active when the blocking condition is removed, the denied inter-

rupt will not be serviced. In other words, the fact that the interrupt

flag was once active but not serviced is not remembered. Every

polling cycle is now.

The polling cycle/LCALL sequence is illustrated in Figure 4-43.

Note that if an interrupt of higher priority level goes active prior

Figure 4-42 Interrupt Control Block

IE / IE2 / IE3 Register

IP / IP2 / IP3 Register

Interrupt Enable Control

Interrupt Priority Control

INTEX0

INTT0

INTEX1

INTT1

INTS0

(RI or TI)

INTT2

(TF2 or T2EX)

INTWDT

INTIF

INTADC

INTEX2

INTEX3

INTEX4

INTS1

INTS2

INTEX5

INTEX6

INTT3

INTT4

High Level Priority

High Polling Priority

Low Level Priority

High Polling Priority

High Level Priority

Low Polling Priority

Low Level Priority

Low Polling Priority

Interrupt Polling

Sequence

EA Register

Global Enable

Individual Enables

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