HMS91C8032 datasheet(21/157 Pages) HYNIX

21 / 157 page

HMS91C8032/97C8032

NOV., 2001 Ver 1.02

4.1 Clock Generation Block

Software can control the system clock speed of HMS91C8032

with the SCMOD register. the SCMOD register determine sys-

tem clock speed and clock source. Figure 4-3 shows the block di-

agram of the system clock generation block.

Guideline on the CPU clock speed

For determining the speed of CPU clock(fCPU), the following

constraints should be satisfied.

The maximum counting rate of timer0~4 in counter mode,

should be less than or equal to (1/6)fCPU

The maximum timer clock rate of timer0~4 in timer mode

should be less than or equal to (1/2)fCPU

NOTE:

SCMOD: SELECT CLOCK MODE. : 80H

SCMOD[2:0]

Select system clock

fxx

fxx / 2

fxx / 4

fxx / 8

fxx / 16

SCSTOP

SCSW

SCMOD2

SCMOD1

SCMOD0

SCMOD.7

Reserved for future use *

SCMOD.6

Reserved for future use *

SCMOD.5

Reserved for future use *

SCSTOP

SCMOD.4

Software control of the main system oscillator. A logic 1 pulls down the main

system oscillator (7.2MHz).

SCSW

SCMOD.3

Software switch control between main system oscillator and sub system oscillator.

A logic 1 switches sub system oscillator (32.768KHz).

SCMOD2

SCMOD.2

See NOTES

SCMOD1

SCMOD.1

See NOTES

SCMOD0

SCMOD.0

See NOTES

Figure 4-2 System Clock Generation Block

fMOSC

(Main Oscillator Clock)

fSOSC

(Sub Oscillator Clock)

SCSTOP

1/2

1/4

1/8

1/16

fCPU

(CPU Clock)

Watchdog Clock

PLL Clock

fOSC

(Oscillator

Clock)

SCSW

S C M O D 1,2,3

fXX

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