HMS91C8032 datasheet(10/157 Pages) HYNIX

10 / 157 page

HMS91C8032/97C8032

NOV., 2001 Ver 1.02

Data memory consists of 7 pages, and each page can store

128bytes. According to the value of RDPG(FCH) and WR-

PG(FDH), HMS9XC8032 selects working memory page. Figure

2-4 shows the generation method of internal data memory ad-

dress. For example, to read from data memory, HMS9XC8032

references the content of RDPG, generates 10bits address and ac-

cesses the corresponding data. The following two cases are

equivalent.

MOV

00H, A

MOV

R0, A

2.3 Special Function Register

Unlike Intel 805X series, HMS9XC8032 has two SFR pages. If

the content of SFRPG (address:FFH) is clear to 00H(01H),

HMS9XC8032 assumes working SFR page to SFR page 0(1).

Byte-addressing only registers in SFR pages have the same ad-

dress in each SFR pages, but bit addressing registers in SFR page

0 and SFR page 1 are different except ACC, B and PSW.

The Port Data registers are located to SFR page1, and the Periph-

eral Control registers to SFR page0. Refer to "4.2 Special Func-

tion Registers" on page 19.

Figure 2-4 Data Memory Address Generation Method

WRPG [2 : 0]

RDPG [2 : 0]

Implied address of instruction

RAM Read Address

RAM Write Address

Figure 2-5 Upper 128bytes of Internal RAM

80H

FFH

No Bit-Addressable Spaces

Figure 2-6 Page0 ~ Page6 of Internal RAM

Reset Value of

Stack Pointer

Bank

Select

Bits

in PSW

Bit-Addressable

Space

(Bit Addresses 0-7F)

4 Banks of

8 Registers

R0-R7

08H

10H

18H

20H

07H

0FH

17H

1FH

2FH

7FH

Reset Value of

Stack Pointer

Bank

Select

Bits

in PSW

Bit-Addressable

Space

(Bit Addresses 0-7F)

4 Banks of

8 Registers

R0-R7

08H

10H

18H

20H

07H

0FH

17H

1FH

2FH

7FH

Page 6

Page 0

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