STAC9704 datasheet(20/49 Pages) HYNIX

20 / 49 page

SigmaTel, Inc.

STAC9704/7

10/02/98

Figure 10. STAC9704/7 Powerdown Timing

SYNC

BIT_CLK

SDATA_OUT

per frame

SDATA_IN

slot2

TAG

Write to

Data

slot2

TAG

per frame

0x20

PR4

Note: BIT_CLK not to scale

BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following

the decode of the write to the Powerdown Register (26h) with PR4. When the AC’97 controller driver is at

the point where it is ready to program the AC-link into its low power mode, slots (1 and 2) are assumed to

be the only valid stream in the audio output frame (all sources of audio input have been neutralized).

The AC’97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9704/7

to this low power mode.

3.2.1 Waking up the AC-link

Once the STAC9704/7 has halted BIT_CLK, there are only two ways to “wake up” the AC-link. Both

methods must be activated by the AC’97 controller. The AC-link protocol provides for a “Cold AC’97

Reset”, and a “Warm AC’97 Reset”. The current power down state would ultimately dictate which

form of reset is appropriate.

Unless a “cold” or “register” reset (a write to the Reset register) is

performed, wherein the AC’97 registers are initialized to their default values, registers will keep their

current state during all power down modes.

Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur

for a minimum of 4 audio frame times following the frame in which the power down was triggered.

When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).

STAC9704 Datasheet(PDF) 20 Page - Hynix Semiconductor