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STAC9704 Datasheet(PDF) 37 Page - Hynix Semiconductor |
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STAC9704 Datasheet(HTML) 37 Page - Hynix Semiconductor |
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37 / 49 page ![]() SigmaTel, Inc. STAC9704/7 37 10/02/98 7.5 Signal Rise and Fall Times - (50pF external load; from 10% to 90% of Vdd) Figure 18: Signal Rise and Fall Times BIT_CLK SDATA_IN Triseclk Tfallclk Trisedin Tfalldin Table 23: Signal Rise and Fall Times PARAMETER SYMBOL MIN TYP MAX UNITS BIT_CLK rise time Triseclk 2 - 6 ns BIT_CLK fall time Tfallclk 2 - 6 ns SDATA_IN rise time Trisedin 2 - 6 ns SDATA_IN fall time Tfalldin 2 - 6 ns 7.6 AC-link Low Power Mode Timing BIT_CLK Stops high in violation of the AC97 specification as noted on the STAC9704/07 errata, but this condition has not caused any known customer problems. Figure 19: AC-link Low Power Mode Timing SYNC BIT_CLK SDATA_OUT SDATA_IN Don't care Slot 1 Slot 2 Write to Data 0x20 PR4 Note: BIT_CLK not to scale Ts2_pdown |
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