2

ICS9179-06

Pin Descriptions

Power Groups

VDD = Power supply for OUTPUT buffers

VDDA= Power supply forAnalog PLL circuitry

Notes:

1.

At power up all sixteen outputs are enabled and active.

2.

OE has a 100K Ohm internal pull-up resistor to keep all outputs active.

3.

The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for

complete platform flexibility.

4.

5.

Subject to design engineering verification of target value.

R

E

B

M

U

N

N

I

PE

M

A

N

N

I

PE

P

Y

TN

O

I

T

P

I

R

C

S

E

D

2E

ON

I

l

a

n

r

e

t

n

i

s

a

H

.

W

O

L

d

l

e

h

n

e

h

w

T

U

O

_

B

F

t

p

e

c

x

e

s

t

u

p

t

u

o

l

l

a

s

e

t

a

t

s

-

i

r

T

.

p

u

-

l

l

u

p

2

0

1

,

9

,

6

,

5)

3

:

0

(

T

U

P

T

U

OT

U

Os

t

u

p

t

u

o

k

c

o

l

c

0

e

t

y

B

M

A

R

D

S

1

0

2

,

9

1

,

6

1

,

5

1)

7

:

4

(

T

U

P

T

U

OT

U

Os

t

u

p

t

u

o

k

c

o

l

c

1

e

t

y

B

M

A

R

D

S

1

4

3

,

3

3

,

0

3

,

9

2)

1

1

:

8

(

T

U

P

T

U

OT

U

Os

t

u

p

t

u

o

k

c

o

l

c

2

e

t

y

B

M

A

R

D

S

1

5

4

,

4

4

,

1

4

,

0

4)

5

1

:

2

1

(

T

U

P

T

U

OT

U

Os

t

u

p

t

u

o

k

c

o

l

c

3

e

t

y

B

M

A

R

D

S

1

2

1T

U

P

N

IN

I.

k

c

o

l

c

e

c

n

e

r

e

f

e

r

r

o

f

t

u

p

n

I

3

1N

I

_

B

FN

I.

t

u

p

n

i

k

c

a

b

d

e

e

F

4

2A

T

A

D

SO

/

II

r

o

f

n

i

p

a

t

a

D

2

y

r

t

i

u

c

r

i

c

C

3

5

2K

L

C

SO

/

II

r

o

f

n

i

p

k

c

o

l

C

2

y

r

t

i

u

c

r

i

c

C

3

7

3T

U

O

_

B

FT

U

O.

N

I

_

B

F

t

u

p

n

i

o

t

t

u

p

t

u

o

k

c

a

b

d

e

e

F

,

1

3

,

1

2

,

7

1

,

1

1

,

7

,

3

6

4

,

2

4

,

8

3

,

5

3

D

D

VR

W

Ps

r

e

f

f

u

b

t

u

p

t

u

o

r

o

f

y

l

p

p

u

s

r

e

w

o

P

V

3

.

3

,

2

3

,

8

2

,

8

1

,

4

1

,

8

,

4

7

4

,

3

4

,

9

3

,

6

3

D

N

GR

W

Ps

r

e

f

f

u

b

t

u

p

t

u

o

r

o

f

d

n

u

o

r

G

2

2A

D

D

VR

W

Ps

e

g

a

t

s

L

L

P

g

o

l

a

n

A

r

o

f

y

l

p

p

u

s

r

e

w

o

P

V

3

.

3

3

2S

D

D

VR

W

PI

r

o

f

y

l

p

p

u

s

r

e

w

o

P

V

3

.

3

2

y

r

t

i

u

c

r

i

c

C

6

2S

D

N

GR

W

PI

r

o

f

d

n

u

o

r

G

2

y

r

t

i

u

c

r

i

c

C

7

2A

D

N

GR

W

Ps

e

g

a

t

s

L

L

P

g

o

l

a

n

A

r

o

f

d

n

u

o

r

G

8

4

,

1C

/

N-

d

e

t

c

e

n

n

o

c

y

l

l

a

n

r

e

t

n

i

t

o

n

e

r

a

s

n

i

P

Ground Groups

GND = Ground supply for OUTPUT buffer

GNDA= Ground supply forAnalog PLL circuitry

Delay Selection Table

4

T

U

P

N

I

l

o

r

t

n

o

C

1

t

i

b

0

e

t

y

B

N

I

_

B

F

l

o

r

t

n

o

C

0

t

i

b

0

e

t

y

B

t

e

g

r

a

T

l

a

n

i

m

o

N

5

o

t

T

U

P

N

I

,

y

a

l

e

D

.

s

n

i

p

N

I

_

B

F

*

0*

0s

n

0

01

s

n

7

.

2

-

10

s

n

0

.

2

+

11

s

n

7

.

0

-