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ICS9179F-06 Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS9179F-06 Datasheet(HTML) 4 Page - Integrated Circuit Systems |
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4 / 8 page ![]() 4 ICS9179-06 Byte 2: OUTPUT Clock Register (Default = 1) Notes: 1 = Enabled; 0 = Disabled, outputs held low T I B# N I PD W PN O I T P I R C S E D 7 t i B5 41 ) t c a n I / t c A ( 5 1 T U P T U O 6 t i B4 41 ) t c a n I / t c A ( 4 1 T U P T U O 5 t i B1 41 ) t c a n I / t c A ( 3 1 T U P T U O 4 t i B0 41 ) t c a n I / t c A ( 2 1 T U P T U O 3 t i B4 31 ) t c a n I / t c A ( 1 1 T U P T U O 2 t i B3 31 ) t c a n I / t c A ( 0 1 T U P T U O 1 t i B0 31 ) e v i t c a n I / e v i t c A ( 9 T U P T U O 0 t i B9 21 ) e v i t c a n I / e v i t c A ( 8 T U P T U O Byte 3: OUTPUT Clock Register Notes: 1 = Enabled; 0 = Disabled, outputs held low T I B# N I PD W PN O I T P I R C S E D 7 t i B- 1 d e v r e s e R 6 t i B- 1 d e v r e s e R 5 t i B- 1 d e v r e s e R 4 t i B- 1 d e v r e s e R 3 t i B- 1 d e v r e s e R 2 t i B- 1 d e v r e s e R 1 t i B- 1 d e v r e s e R 0 t i B- 1 d e v r e s e R ICS9179-06 Power Management The values below are estimates of target specifications. n o i t i d n o C n o i t p m u s n o c y l p p u s V 3 . 3 x a M s d a o l p a c e t e r c s i d x a M V 5 6 4 . 3 = D D V D N G r o D D V = s t u p n i c i t a t s l l A e d o M k c o l C o N ) D N G r o 1 D D V - N I _ F U B ( I2 e v i t c A y r t i u c r i C C A m 0 3 z H M 6 6 e v i t c A ) z H M 6 6 . 6 6 = N I _ F U B ( A m 0 5 1 z H M 0 0 1 e v i t c A ) z H M 0 0 . 0 0 1 = N I _ F U B ( A m 0 8 1 Note: PWD = Power-Up Default Byte 0: OUTPUT Clock Register (default = 0) Notes: 2 = Default = 0; 1 = Delay element enabled, 0 = No delay path. T I B# N I PD W PN O I T P I R C S E D 7 t i B- 0 d e v r e s e R 6 t i B- 0 d e v r e s e R 5 t i B- 0 d e v r e s e R 4 t i B- 0 d e v r e s e R 3 t i B- 0 d e v r e s e R 2 t i B- 0 d e v r e s e R 1 t i B 2 2 10 l o r t n o C w e k S T U P N I k c o l C 0 t i B 2 3 10 l o r t n o C w e k S N I B F Serial Configuration Command Bitmaps Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 1: OUTPUT Clock Register T I B# N I PD W PN O I T P I R C S E D 7 t i B0 21 ) t c a n I / t c A ( 7 T U P T U O 6 t i B9 11 ) t c a n I / t c A ( 6 T U P T U O 5 t i B 6 11 ) t c a n I / t c A ( 5 T U P T U O 4 t i B5 11 ) t c a n I / t c A ( 4 T U P T U O 3 t i B 0 11 ) t c a n I / t c A ( 3 T U P T U O 2 t i B9 1 ) t c a n I / t c A ( 2 T U P T U O 1 t i B6 1 ) t c a n I / t c A ( 1 T U P T U O 0 t i B5 1 ) t c a n I / t c A ( 0 T U P T U O Note: PWD = Power-Up Default |
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