2

ICS9248-65

Pin Descriptions

Pin number Pin name

Type

Description

1,2

REF

Output

3.3V, 14.318 MHz reference clock output.

3, 9, 17, 24,

28, 34

VDD

Power

3.3 V power for clock outputs.

4

X1

Input

14.318 MHz crystal input

5

X2

Output

14.318 MHz crystal output

6,14, 20, 26,

33, 45, 48

GND

Power

Ground for clock outputs

7

PCICLK_F

Output

3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#

8,10,11,12,13,

15,16,18,19

PCICLK (1:9)

Output

3.3 V PCI clock outputs, generating timing requirements for

21,22,23

3V66

Output

3.3 V 66 MHz clock output, fixed frequency clock typically used with AGP

25

SEL

133/100#

Input

Control for the frequency of clocks at the CPU output pins. If logic "0" is used the

100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is

selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.

27

48 MHz

Output

3.3 V 48 MHz clock output, fixed frequency clock typically used with USB

devices

29,30

SEL (0:1)

Input

Frequency select pin , logic input.

31

SPREAD#

Output

Power-on spread spectrum enable option. Active low = spread spectrum clocking

enable. Active high = spread spectrum clocking disable.

32

PD#

Input

Asynchronous active low input pin used to power down the device into a low

power state. The internal clocks are disabled and the VCO and the crystal are

stopped.

35,39

GNDLCPU

Power

Ground for the CPU and Host clock outputs

36,37,40

CPUCLK

(0:2)

0utput

2.5 V CPU and Host clock outputs

38,41

VDDLCPU

Power

2.5 V power for the CPU and Host clock outputs

42

GNDLCPU/2

Power

Ground for the CPU and Host clock outputs

43

CPU/2

Output

Output running at 1/2 CPU clock frequency.Synchronous to the CPU outputs.

44

VDDLCPU/2

Power

2.5 V power for the CPU/2 clock outputs

46

IOAPIC(0:1)

Output

2.5V fixed 16.6 MHz IOAPIC clock outputs

47

VDDIOAPIC

Power

2.5V power for IOAPIC clock

The ICS9248-65 is a main clock synthesizer chip for Pentium

II based systems using Rambus Interface DRAMs. This chip

provides all the clocks required for such a system when used

with a Direct Rambus Clock Generator(DRCG) chip such as

theICS9211-01.

Spread Spectrum may be enabled by driving the SPREAD#

pin active. Spread spectrum typically reduces system EMI by

8dB to 10dB. This simplifies EMI qualification without

resorting to board design iterations or costly shielding. The

ICS9248-65 employs a proprietary closed loop design, which

tightly controls the percentage of spreading over process

and temperature variations.

The CPU/2 clocks are inputs to the DRCG.

General Description

Power Groups:

VDDREF,GNDREF=REF,X1,X2

GNDPCI,VDDPCI=PCICLK

VDD66,GND66=3V66

VDD48,GND48=48MHz

VDDCOR,GNDCOR=PLLCore

VDDLCPU/2,GNDLCPU/2=CPU/2

VDDLIOAPIC,GNDIOAPIC=IOAPIC