AD5539

–9–

REV. B

Figures 21 and 22 show the small and large signal pulse re-

sponses of the general purpose inverter circuit of Figure 17, with

Ω and C

Figure 21. Small Signal Pulse Response of the (Figure 17)

Inverter Circuit; Vertical Scale: 50 mV/div; Horizontal

Scale: 5 ns/div

Figure 22. Large Signal Response of the (Figure 17)

Inverter Circuit; Vertical Scale: 200 mV/div, Horizontal

Scale: 5 ns/div

and to achieve a single pole response free of overshoot

–3 dB frequency

=

1

2

π R2 C

LEAD









connected between Pin 12 and the summing junction, as shown

in Figure 23. Pin 12 provides a separately buffered version of

the output signal. Connecting the lead capacitor here avoids the

excess output-stage phase shift and subsequent oscillation prob-

lems (at approx. 350 MHz) which would otherwise occur when

2 pF.

Figure 24 shows the response of the circuit of Figure 23 for each

circuit to further tailor its response, but, in this case, the results

to the output, as was done in Figure 17.

Capacitor Connected to Pin 12

Figure 24. Response of the Circuit of Figure 23 with

A General Purpose Voltage Follower Circuit

Noninverting (voltage follower) circuits pose an additional com-

plication, in that when a lag network is used, the source imped-

ance will affect the noise gain. In addition, the slightly greater

bandwidth of the noninverting configuration makes any excess

phase shift due to the output stage more of a problem.

nected normally (across the feedback resistor – Figure 25) will

require a source resistance of 200

Ω or greater to prevent UHF

oscillation; the extra source resistance provides some damping

as well as increasing the noise gain. The frequency response plot

of Figure 26 shows that the highest –3 dB frequency of all the

applications circuits can be achieved using this connection, un-

fortunately, at the expense of a noise gain of 14.2.

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