ADG466/ADG467

–5–

REV. 0

CIRCUIT INFORMATION

Figure 7 below shows a simplified schematic of a channel

protector circuit. The circuit is made up of four MOS transis-

tors—two NMOS and two PMOS. One of the PMOS devices

does not lie directly in the signal path but is used to connect the

source of the second PMOS device to its backgate. This has the

effect of lowering the threshold voltage and so increasing the

input signal range of the channel for normal operation. The

source and backgate of the NMOS devices are connected for the

same reason. During normal operation the channel protectors

have a resistance of 60

Ω typ. The channel protectors are very

low power devices, and even under fault conditions the supply

current is limited to sub micro-ampere levels. All transistors are

dielectrically isolated from each other using a trench isolation

method. This makes it impossible to latch up the channel

protectors. For an explanation, see “Trench Isolation” section.

NMOS

PMOS

PMOS

NMOS

Figure 7. The Channel Protector Circuit

Overvoltage Protection

When a fault condition occurs on the input of a channel

protector, the voltage on the input has exceeded some threshold

voltage set by the supply rail voltages. The threshold voltages

are related to the supply rails as follows. For a positive overvolt-

threshold voltage of the NMOS transistor (1.5 V typ). In the

case of a negative overvoltage the threshold voltage is given by

device (2 V typ). If the input voltage exceeds these threshold

voltages, the output of the channel protector (no load) is

clamped at these threshold voltages. However, the channel

protector output will clamp at a voltage that is inside these

thresholds if the output is loaded. For example with an output

load of 1 k

Ω, V

∆V = 15 V – 1.5 V – 0.6 V = 12.9 V

where

∆V is due to I × R voltage drop across the channels of the

MOS devices (see Figure 9). As can be seen from Figure 9, the

current during fault condition is determined by the load on the

fault current is limited to the nano-ampere level.

Figures 8, 10 and 11 show the operating conditions of the signal

path transistors during various fault conditions. Figure 8 shows

how the channel protectors operate when a positive overvoltage

is applied to the channel protector.

NMOS

PMOS

NMOS

POSITIVE

OVERVOLTAGE

(+20V)

(+13.5V)

NON-

SATURATED

NON-

SATURATED

SATURATED

Figure 8. Positive Overvoltage on the Channel Protector

The first NMOS transistor goes into a saturated mode of

operation as the voltage on its Drain exceeds the Gate voltage

Figure 9. The potential at the source of the NMOS device is

mode of operations.

When a negative overvoltage is applied to the channel protector

circuit, the PMOS transistor enters a saturated mode of opera-

low. As in the case of the positive overvoltage, the other MOS

devices are nonsaturated.

NMOS

PMOS

NMOS

NEGATIVE

OVERVOLTAGE

(–20V)

(–13V)

NEGATIVE

OVERVOLTAGE

(–20V)

NON-

SATURATED

NON-

SATURATED

SATURATED

Figure 10. Negative Overvoltage on the Channel Protector

N +

P –

N +

N +

(+20V)

(+13.5V)

OVERVOLTAGE

OPERATION

(SATURATED)

EFFECTIVE

SPACE CHARGE

REGION

N CHANNEL

NMOS

PMOS

NONSATURATED

OPERATION

∆V

Figure 9. Positive Overvoltages Operation of the Channel Protector

OBSOLETE