ADG466/ADG467

–6–

REV. 0

The channel protector is also functional when the supply rails

are down (e.g., power failure) or momentarily unconnected

(e.g., rack system). This is where the channel protector has an

advantage over more conventional protection methods such as

limited to subnano-ampere levels (see Figure 11).

NMOS

PMOS

NMOS

POSITIVE OR

NEGATIVE

OVERVOLTAGE

(0V)

OFF

OFF

OFF

Figure 11. Channel Protector Supplies Equal to Zero Volts

TRENCH ISOLATION

The MOS devices that make up the channel protector are

isolated from each other by an oxide layer (trench) (see Figure

12). When the NMOS and PMOS devices are not electrically

isolated from each other, there exists the possibility of “latch-

up” caused by parasitic junctions between CMOS transistors.

Latch-up is caused when P-N junctions that are normally

reverse biased become forward biased, causing large currents to

flow, which can be destructive.

CMOS devices are normally isolated from each other by

Junction Isolation. In Junction Isolation, the N and P wells of the

CMOS transistors form a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward biased. A Silicon-Controlled Rectifier

(SCR) type circuit is formed by the two transistors causing a

significant amplification of the current that, in turn, leads to

latch-up. With Trench Isolation, this diode is removed; the

result is a latch-up proof circuit.

P-CHANNEL

P+

P+

N–

N-CHANNEL

N+

N+

P–

T

R

E

N

C

H

T

R

E

N

C

H

T

R

E

N

C

H

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

Figure 12. Trench Isolation

APPLICATIONS INFORMATION

Overvoltage and Power Supply Sequencing Protection

The ADG466 and ADG467 are ideal for use in applications

where input overvoltage protection is required and correct

power supply sequencing cannot always be guaranteed. The

overvoltage protection ensures that the output voltage of the

channel protector will not exceed the threshold voltages set by

the supplies (see “Circuit Information”) when there is an

overvoltage on the input. When the input voltage does not

exceed these threshold voltages, the channel protector behaves

like a series resistor (60

Ω typ). The resistance of the channel

protector does vary slightly with operating conditions (see

“Typical Performance Graphs”).

The power sequencing protection is afforded by the fact that

when the supplies to the channel protector are not connected,

the channel protector becomes a high resistance device. Under

this condition all transistors in the channel protector are off and

the only currents that flow are leakage currents, which are at the

µA level.

+5V

–5V

EDGE

CONNECTOR

ADG466

ADC

CONTROL

LOGIC

ANALOG IN

–2.5V TO +2.5V

LOGIC

LOGIC

GND

Figure 13. Overvoltage and Power Supply Sequencing

Protection

Figure 13 shows a typical application that requires overvoltage

and power supply sequencing protection. The application shows

a Hot-Insertion rack system. This involves plugging a circuit

board or module into a live rack via an edge connector. In this

type of application it is not possible to guarantee correct power

supply sequencing. Correct power supply sequencing means

that the power supplies should be connected before any external

signals. Incorrect power sequencing can cause a CMOS device

to “latch up.” This is true of most CMOS devices regardless of

the functionality. RC networks are used on the supplies of the

channel protector (Figure 13) to ensure that the rest of the

circuitry is powered up before the channel protectors. In this

way, the outputs of the channel protectors are clamped well

ensure that the supplies on the channel protector never exceed

the supply rails of the board when it is being disconnected.

Again this ensures that signals on the inputs of the CMOS

devices never exceed the supplies.

OBSOLETE